coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-10	soc/intel/tigerlake: Maintain consistent tab in iomap.h	Subrata Banik
2020-07-12	soc/intel/tigerlake: Add Type-C IOM base address and size macro	John Zhao
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-12	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao
2020-02-17	src/soc/tigerlake: Accomodate JSP specific changes in iomap.h	Meera Ravindranath
2020-01-15	soc/intel/tigerlake: Update header files	Ravi Sarawadi
2020-01-10	soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper	Subrata Banik
2019-11-09	soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik