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path: root/src/soc/intel/tigerlake/include
AgeCommit message (Expand)Author
2020-10-24{cpu,soc}/intel: deduplicate cpu codeMichael Niewöhner
2020-10-21soc/intel: convert XTAL frequency constant to KconfigMichael Niewöhner
2020-10-05soc: move mainboard_get_dram_part_num prototype to memory_info.hNick Vaccaro
2020-10-05mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro
2020-10-03soc/intel: Make use of PMC low power program from common blockSubrata Banik
2020-09-25soc/intel/tigerlake: Remove extra '_' from GPIO PIN nameSubrata Banik
2020-09-21src/soc/intel: Drop unneeded empty linesElyes HAOUAS
2020-09-11soc/intel/tigerlake: Clean up systemagent.hSubrata Banik
2020-09-10soc/intel/tigerlake: Maintain consistent tab in iomap.hSubrata Banik
2020-09-04soc/intel/tigerlake: Remove unused PID_SDX macroSubrata Banik
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
2020-08-26soc/intel/tigerlake: Rename pch_init() codeAlexey Buyanov
2020-08-12soc/intel/tigerlake: Add IRQs for LPSS uartPatrick Rudolph
2020-08-09soc/intel/{icl.tgl,jsl}: Remove SMRAM register programmingAamir Bohra
2020-08-06soc/intel/tigerlake: add common routine for DDR initNick Vaccaro
2020-07-29soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dBDuncan Laurie
2020-07-26soc/intel/tigerlake: Disable CPU PCIe in FSPShaunak Saha
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
2020-07-25soc/intel/tigerlake: Update Pkg C-State latenciesRavi Sarawadi
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
2020-07-12soc/intel/tigerlake: Add Type-C IOM base address and size macroJohn Zhao
2020-07-07soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus masterJohn Zhao
2020-05-26soc/intel/tigerlake: Disable VMDWonkyu Kim
2020-05-22soc/intel/tigerlake: Add definition for PMC EPOCDuncan Laurie
2020-05-20soc/intel/tigerlake: Move PMC PCI resources under PMC deviceTim Wawrzynczak
2020-05-20tigerlake: update processor power limits configurationSumeet R Pawnikar
2020-05-18soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1EnJohn Zhao
2020-05-14soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()Furquan Shaikh
2020-05-14soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4GFurquan Shaikh
2020-05-12soc/intel/tigerlake: Correct IRQ interruptWonkyu Kim
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-11soc/intel/tigerlake: Update C-State infoWonkyu Kim
2020-05-06soc/intel/tgl: Synchronize GPIO ASL table with Linux kernelShaunak Saha
2020-05-06soc/intel/tigerlake: Print HPR_CAUSE0 registerderek.huang
2020-05-04soc/intel/tigerlake: Update interrupt settingWonkyu Kim
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
2020-04-17soc/intel/tigerlake: Remove eMMC/SD supportDuncan Laurie
2020-04-10soc/intel/tigerlake: Add support to initialize DDR4 MemoryVarun Joshi
2020-04-07soc/intel/tigerlake: Allow mainboard to override DRAM part numberMarco Chen
2020-04-06soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons
2020-04-02soc/intel/tigerlake: Add macros and SPD information for DDR4Furquan Shaikh
2020-04-02soc/intel/tigerlake: Reorganize memory initialization supportFurquan Shaikh
2020-04-01soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra
2020-03-21soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition properSubrata Banik
2020-03-19soc/intel/tigerlake: add support to read SPD data from SMBusRonak Kanabar
2020-03-19soc/intel/tigerlake: Update header to avoid compilation issueMaulik V Vaghela
2020-03-18soc/intel/tigerlake: Correct number of gpio group for Jasper LakeMaulik V Vaghela
2020-03-18soc: Remove copyright noticesPatrick Georgi
2020-03-12soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI tableJohn Zhao
2020-03-07intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registersMichael Niewöhner