| Age | Commit message (Expand) | Author |
|---|
| 2020-05-06 | soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel | Shaunak Saha |
| 2020-05-06 | soc/intel/tigerlake: Print HPR_CAUSE0 register | derek.huang |
| 2020-05-04 | soc/intel/tigerlake: Update interrupt setting | Wonkyu Kim |
| 2020-05-02 | acpi: Move ACPI table support out of arch/x86 (3/5) | Furquan Shaikh |
| 2020-04-17 | soc/intel/tigerlake: Remove eMMC/SD support | Duncan Laurie |
| 2020-04-10 | soc/intel/tigerlake: Add support to initialize DDR4 Memory | Varun Joshi |
| 2020-04-07 | soc/intel/tigerlake: Allow mainboard to override DRAM part number | Marco Chen |
| 2020-04-06 | soc/intel/tigerlake: Use SPDX for GPL-2.0-only files | Angel Pons |
| 2020-04-02 | soc/intel/tigerlake: Add macros and SPD information for DDR4 | Furquan Shaikh |
| 2020-04-02 | soc/intel/tigerlake: Reorganize memory initialization support | Furquan Shaikh |
| 2020-04-01 | soc/intel/tigerlake: Remove Jasper Lake SoC references | Aamir Bohra |
| 2020-03-21 | soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition proper | Subrata Banik |
| 2020-03-19 | soc/intel/tigerlake: add support to read SPD data from SMBus | Ronak Kanabar |
| 2020-03-19 | soc/intel/tigerlake: Update header to avoid compilation issue | Maulik V Vaghela |
| 2020-03-18 | soc/intel/tigerlake: Correct number of gpio group for Jasper Lake | Maulik V Vaghela |
| 2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
| 2020-03-12 | soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table | John Zhao |
| 2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers | Michael Niewöhner |
| 2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected | Michael Niewöhner |
| 2020-03-03 | soc/intel/tigerlake: Add Jasper lake GPIO support | Ronak Kanabar |
| 2020-03-03 | src/soc/tigerlake: Add memory configuration support for Jasper Lake | Meera Ravindranath |
| 2020-02-27 | soc/intel/tigerlake: Update FSP params for Jasper Lake | Maulik V Vaghela |
| 2020-02-19 | soc/tigerlake: Add IRQ header and ACPI support for JSP | Meera Ravindranath |
| 2020-02-17 | src/intel: Define HFSTS3 register | Sridhar Siricilla |
| 2020-02-17 | src/soc/tigerlake: Accomodate JSP specific changes in iomap.h | Meera Ravindranath |
| 2020-02-09 | soc/intel/tigerlake: add memory configuration support | Nick Vaccaro |
| 2020-02-09 | soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC | Sridhar Siricilla |
| 2020-02-04 | soc/intel: Add get_pmbase | Eugene Myers |
| 2020-01-25 | soc/intel/tigerlake: Fix GPIO communities | Shaunak Saha |
| 2020-01-22 | soc/intel/tigerlake: Update GPIO config | Ravi Sarawadi |
| 2020-01-22 | soc/intel/tigerlake: Update interrupt info | Wonkyu Kim |
| 2020-01-18 | soc/intel/tigerlake: Update pci dev definition | Wonkyu Kim |
| 2020-01-15 | soc/intel/tigerlake: Update header files | Ravi Sarawadi |
| 2020-01-10 | soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper | Subrata Banik |
| 2020-01-09 | sb/intel/common: Add smbus_set_slave_addr() | Kyösti Mälkki |
| 2019-12-16 | soc/intel/tigerlake: Pick correct pmc base reg from pch type | Maulik V Vaghela |
| 2019-11-22 | intel/smm: Provide common smm_relocation_params | Kyösti Mälkki |
| 2019-11-15 | soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init() | Subrata Banik |
| 2019-11-09 | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik |
| 2019-11-09 | soc/intel/tigerlake/romstage: Do initial SoC commit till romstage | Subrata Banik |
| 2019-11-09 | soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock | Subrata Banik |
