coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-03-01	soc/intel: Drop `bootblock_cpu_init()` function	Angel Pons
2021-03-01	soc/intel: Drop `romstage_pch_init()` function	Angel Pons
2021-03-01	soc/intel: Factor out common smbus.h	Angel Pons
2021-03-01	soc/intel: Factor out common gpe.h	Angel Pons
2021-02-22	soc/intel/tigerlake: Add CrashLog implementation for intel TGL	Francois Toguo
2021-02-16	soc/intel: Drop aliases on MMCONF_BASE_ADDRESS	Kyösti Mälkki
2021-01-25	soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver	Furquan Shaikh
2021-01-11	soc/intel/{icl,tgl,jsl,ehl}: add LPIT support	Michael Niewöhner
2021-01-08	soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports	John Zhao
2020-12-08	src/soc/intel/tigerlake: Add SPI DMI Destination ID	Srinidhi N Kaushik
2020-11-30	soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices	Tim Wawrzynczak
2020-11-13	soc/intel/tigerlake: Add code for early tcss	Brandon Breitenstein
2020-10-24	{cpu,soc}/intel: deduplicate cpu code	Michael Niewöhner
2020-10-21	soc/intel: convert XTAL frequency constant to Kconfig	Michael Niewöhner
2020-10-05	soc: move mainboard_get_dram_part_num prototype to memory_info.h	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-10-03	soc/intel: Make use of PMC low power program from common block	Subrata Banik
2020-09-25	soc/intel/tigerlake: Remove extra '_' from GPIO PIN name	Subrata Banik
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-09-11	soc/intel/tigerlake: Clean up systemagent.h	Subrata Banik
2020-09-10	soc/intel/tigerlake: Maintain consistent tab in iomap.h	Subrata Banik
2020-09-04	soc/intel/tigerlake: Remove unused PID_SDX macro	Subrata Banik
2020-09-02	soc/intel/tigerlake: Add mainboard hook for overriding SoC config	Jes Klinke
2020-08-26	soc/intel/tigerlake: Rename pch_init() code	Alexey Buyanov
2020-08-12	soc/intel/tigerlake: Add IRQs for LPSS uart	Patrick Rudolph
2020-08-09	soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming	Aamir Bohra
2020-08-06	soc/intel/tigerlake: add common routine for DDR init	Nick Vaccaro
2020-07-29	soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dB	Duncan Laurie
2020-07-26	soc/intel/tigerlake: Disable CPU PCIe in FSP	Shaunak Saha
2020-07-26	src: Remove extra lines in license header	Elyes HAOUAS
2020-07-25	soc/intel/tigerlake: Update Pkg C-State latencies	Ravi Sarawadi
2020-07-14	src: Remove unused 'include <stdint.h>	Elyes HAOUAS
2020-07-12	soc/intel/tigerlake: Add Type-C IOM base address and size macro	John Zhao
2020-07-07	soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master	John Zhao
2020-05-26	soc/intel/tigerlake: Disable VMD	Wonkyu Kim
2020-05-22	soc/intel/tigerlake: Add definition for PMC EPOC	Duncan Laurie
2020-05-20	soc/intel/tigerlake: Move PMC PCI resources under PMC device	Tim Wawrzynczak
2020-05-20	tigerlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh
2020-05-12	soc/intel/tigerlake: Correct IRQ interrupt	Wonkyu Kim
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-11	soc/intel/tigerlake: Update C-State info	Wonkyu Kim
2020-05-06	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha
2020-05-06	soc/intel/tigerlake: Print HPR_CAUSE0 register	derek.huang
2020-05-04	soc/intel/tigerlake: Update interrupt setting	Wonkyu Kim
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-04-17	soc/intel/tigerlake: Remove eMMC/SD support	Duncan Laurie
2020-04-10	soc/intel/tigerlake: Add support to initialize DDR4 Memory	Varun Joshi