coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-10-24	{cpu,soc}/intel: deduplicate cpu code	Michael Niewöhner
2020-10-21	soc/intel: convert XTAL frequency constant to Kconfig	Michael Niewöhner
2020-10-05	soc: move mainboard_get_dram_part_num prototype to memory_info.h	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-10-03	soc/intel: Make use of PMC low power program from common block	Subrata Banik
2020-09-25	soc/intel/tigerlake: Remove extra '_' from GPIO PIN name	Subrata Banik
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-09-11	soc/intel/tigerlake: Clean up systemagent.h	Subrata Banik
2020-09-10	soc/intel/tigerlake: Maintain consistent tab in iomap.h	Subrata Banik
2020-09-04	soc/intel/tigerlake: Remove unused PID_SDX macro	Subrata Banik
2020-09-02	soc/intel/tigerlake: Add mainboard hook for overriding SoC config	Jes Klinke
2020-08-26	soc/intel/tigerlake: Rename pch_init() code	Alexey Buyanov
2020-08-12	soc/intel/tigerlake: Add IRQs for LPSS uart	Patrick Rudolph
2020-08-09	soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming	Aamir Bohra
2020-08-06	soc/intel/tigerlake: add common routine for DDR init	Nick Vaccaro
2020-07-29	soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dB	Duncan Laurie
2020-07-26	soc/intel/tigerlake: Disable CPU PCIe in FSP	Shaunak Saha
2020-07-26	src: Remove extra lines in license header	Elyes HAOUAS
2020-07-25	soc/intel/tigerlake: Update Pkg C-State latencies	Ravi Sarawadi
2020-07-14	src: Remove unused 'include <stdint.h>	Elyes HAOUAS
2020-07-12	soc/intel/tigerlake: Add Type-C IOM base address and size macro	John Zhao
2020-07-07	soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master	John Zhao
2020-05-26	soc/intel/tigerlake: Disable VMD	Wonkyu Kim
2020-05-22	soc/intel/tigerlake: Add definition for PMC EPOC	Duncan Laurie
2020-05-20	soc/intel/tigerlake: Move PMC PCI resources under PMC device	Tim Wawrzynczak
2020-05-20	tigerlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh
2020-05-12	soc/intel/tigerlake: Correct IRQ interrupt	Wonkyu Kim
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-11	soc/intel/tigerlake: Update C-State info	Wonkyu Kim
2020-05-06	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha
2020-05-06	soc/intel/tigerlake: Print HPR_CAUSE0 register	derek.huang
2020-05-04	soc/intel/tigerlake: Update interrupt setting	Wonkyu Kim
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-04-17	soc/intel/tigerlake: Remove eMMC/SD support	Duncan Laurie
2020-04-10	soc/intel/tigerlake: Add support to initialize DDR4 Memory	Varun Joshi
2020-04-07	soc/intel/tigerlake: Allow mainboard to override DRAM part number	Marco Chen
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-02	soc/intel/tigerlake: Add macros and SPD information for DDR4	Furquan Shaikh
2020-04-02	soc/intel/tigerlake: Reorganize memory initialization support	Furquan Shaikh
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-21	soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition proper	Subrata Banik
2020-03-19	soc/intel/tigerlake: add support to read SPD data from SMBus	Ronak Kanabar
2020-03-19	soc/intel/tigerlake: Update header to avoid compilation issue	Maulik V Vaghela
2020-03-18	soc/intel/tigerlake: Correct number of gpio group for Jasper Lake	Maulik V Vaghela
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-12	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao
2020-03-07	intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers	Michael Niewöhner