coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-06	soc/intel/tigerlake: Print HPR_CAUSE0 register	derek.huang
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-02-04	soc/intel: Add get_pmbase	Eugene Myers
2020-01-18	soc/intel/tigerlake: Update chip files	Ravi Sarawadi
2019-12-19	src/soc/intel: Remove unused <stdlib.h>	Elyes HAOUAS
2019-12-11	soc/intel/tigerlake: add soc implementation for ETR address API	Aamir Bohra
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik