| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-02-09 | soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_messa... | Sridhar Siricilla |
| 2019-11-09 | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |