coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-16	soc/intel/tigerlake: Support ISH	li feng
2020-03-15	soc/intel/tigerlake: Update Cpu Ratio settings	Srinidhi N Kaushik
2020-03-15	soc/intel/tigerlake: Configure Vmx support using Kconfig	John Zhao
2020-03-12	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao
2020-03-12	soc/intel/tigerlake: Enable HDA through dev_enabled	Srinidhi N Kaushik
2020-03-11	soc/intel/tigerlake: Save DIMM info by available nodes	Jamie Ryu
2020-03-11	soc/intel/tigerlake: Correct FSP log interface	Ronak Kanabar
2020-03-07	soc/intel/tigerlake: Avoid NULL pointer dereference	John Zhao
2020-03-02	soc/tigerlake: Correct FSP log interface	Wonkyu Kim
2020-03-01	soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig	Subrata Banik
2020-02-27	soc/intel/tigerlake: Add display related UPD configs for Jasper Lake	Aamir Bohra
2020-02-27	soc/intel/tigerlake: Update FSP params for Jasper Lake	Maulik V Vaghela
2020-02-17	soc/intel/tigerlake: Enable Audio on TGL	Srinidhi N Kaushik
2020-02-01	soc/intel/tigerlake: Configure TCSS xHCI and xDCI	Wonkyu Kim
2020-01-29	soc/intel/tigerlake: Disable image clocks	Wonkyu Kim
2020-01-28	soc/intel/tigerlake: Enable DP ports according to board design	Wonkyu Kim
2020-01-25	soc/intel/tigerlake: Configure ClkReq according to mainboard design	Wonkyu Kim
2020-01-22	soc/intel/tigerlake: Update fsp_params for TGL	Srinidhi N Kaushik
2020-01-13	soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig	Maulik V Vaghela
2019-11-09	soc/intel/tigerlake/romstage: Do initial SoC commit till romstage	Subrata Banik