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path: root/src/soc/intel/tigerlake/romstage
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2020-03-15soc/intel/tigerlake: Update Cpu Ratio settingsSrinidhi N Kaushik
Add config to override CpuRatio or setting CpuRatio to allowed maximum processor non-turbo ratio. BUG=151175469 BRANCH=none TEST=Build and boot tglrvp and observe there is no extra reset in meminit. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15soc/intel/tigerlake: Configure Vmx support using KconfigJohn Zhao
Change VmxEnable UPD value based on Kconfig ENABLE_VMX BUG=None TEST=Built image and booted to kernel. Change-Id: I725474643193223865a135813cf882fd7636d24a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-12soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI tableJohn Zhao
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table. BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-12soc/intel/tigerlake: Enable HDA through dev_enabledSrinidhi N Kaushik
Check for dev enabled status for HDA controller and update the UPD accordingly. BUG=151174264 BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11soc/intel/tigerlake: Save DIMM info by available nodesJamie Ryu
TEST=Verified that dmidecode produces output identical to private repo Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11soc/intel/tigerlake: Correct FSP log interfaceRonak Kanabar
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly. BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-07soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference if dev did not point to the audio device. BUG=CID 1420208 TEST=Built image successfully. Change-Id: I2a62da44c7044f9dc281eae0949f7f7b612ab238 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-02soc/tigerlake: Correct FSP log interfaceWonkyu Kim
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-01soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by KconfigSubrata Banik
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-27soc/intel/tigerlake: Add display related UPD configs for Jasper LakeAamir Bohra
TEST=Build dedede board Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-27soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela
Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-17soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-01soc/intel/tigerlake: Configure TCSS xHCI and xDCIWonkyu Kim
Configure xHCI, xDCI according to board design BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-29soc/intel/tigerlake: Disable image clocksWonkyu Kim
TGL FSP does just pin mux for image clock pins by UPD and image clocks are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder. Disable image clocks by UPD for bypassing FSP pin mux and do pin mux in gpio.c according to board design. BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28soc/intel/tigerlake: Enable DP ports according to board designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia6e9271a11a1f9e6f98923772219ccc1e7daecda Reviewed-on: https://review.coreboot.org/c/coreboot/+/38528 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25soc/intel/tigerlake: Configure ClkReq according to mainboard designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/tigerlake: Update fsp_params for TGLSrinidhi N Kaushik
Add initial fsp upd settings for TGL, both romstage and ramstage upd's to support basic build and boot of TGL RVP. - Add Silicon upd settings which includes * Serial IO/UART settings * Graphics settings * USB2/USB3 settings - Add Romstage upd settings which includes * Pcie Root port settings * IGD initialization * Hyper Threading settings * SMBus controller settings * Debug probe settings BUG=none BRANCH=none TEST=Build and boot Tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-13soc/intel/tigerlake: Select correct fsp_param as per SoC KconfigMaulik V Vaghela
New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake has differences compared to Tigerlake. Thus renaming fsp_params.c to fsp_params_tgl.c to point out correct file as per soc selected. Also adding new file for fsp_param_jsl for Jasperlake SoC and currently its the copy of fsp_param_tgl. TODO: update files with correct fsp_params Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/romstage: Do initial SoC commit till romstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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