coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-08	soc/intel/tigerlake: Add SMRR Locking support	Tim Wawrzynczak
2020-08-09	soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming	Aamir Bohra
2020-06-02	src: Remove unused '#include <cpu/x86/lapic.h>'	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	src: Remove unused 'include <cpu/x86/cache.h>'	Elyes HAOUAS
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-12-19	src: Use '#include <smp/node.h>' when appropriate	Elyes HAOUAS
2019-11-27	soc/intel/tigerlake: Fix smm_relocation_params	Kyösti Mälkki
2019-11-22	intel/smm: Provide common smm_relocation_params	Kyösti Mälkki
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik