coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-07-25	soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU	Sumeet R Pawnikar
2020-07-25	soc/intel/tigerlake: Update Tiger Lake SA IDs	Derek Huang
2020-06-22	mb/google/volteer: Override power limits with SKU-specific limits	Tim Wawrzynczak
2020-05-28	soc/intel/common: Improve Type16 SMBIOS tables	Patrick Rudolph
2020-05-20	soc/intel/tigerlake: Move PMC PCI resources under PMC device	Tim Wawrzynczak
2020-05-20	tigerlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-12	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik