coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-25	soc/intel/{jsl,tgl}: Refactor gpio_op.asl	Subrata Banik
2020-09-24	soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffload	John Zhao
2020-09-23	soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths	Jamie Ryu
2020-09-22	Revert "soc/intel: Refactor do_global_reset() function"	Furquan Shaikh
2020-09-21	src/soc/intel: Drop unneeded empty lines	Elyes HAOUAS
2020-09-21	soc/intel: Refactor do_global_reset() function	Subrata Banik
2020-09-21	soc/intel: rename get_prmrr_size	Michael Niewöhner
2020-09-19	soc/intel/common/block/cse: Refactor cse_request_global_reset() function	Subrata Banik
2020-09-17	mb/volteer: Select USE_CAR_NEM_ENHANCED_V2 for Tigerlake QS based	Shreesh Chhabbi
2020-09-14	soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h	Subrata Banik
2020-09-14	soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB	Anil Kumar
2020-09-14	soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake	Shreesh Chhabbi
2020-09-11	soc/intel/tigerlake: Clean up systemagent.h	Subrata Banik
2020-09-10	soc/intel/tigerlake: Maintain consistent tab in iomap.h	Subrata Banik
2020-09-08	soc/intel/tigerlake: Skip GPIO configuration from FSP	Srinidhi N Kaushik
2020-09-08	soc/intel/tigerlake: Add SMRR Locking support	Tim Wawrzynczak
2020-09-06	soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default	Michael Niewöhner
2020-09-04	soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_CO...	Elyes HAOUAS
2020-09-04	soc/intel/tigerlake: Remove unused PID_SDX macro	Subrata Banik
2020-09-02	soc/intel/tigerlake: Add mainboard hook for overriding SoC config	Jes Klinke
2020-08-28	soc/intel/tigerlake: add ddr4-spd-empty.hex	Aaron Durbin
2020-08-28	util: Add memory parts needed by zork boards	Rob Barnes
2020-08-28	util/gen_spd: translate DeviceBusWidth to die bus width	Nick Vaccaro
2020-08-28	util: rename lp4x spds to include "lp4x-" in name	Nick Vaccaro
2020-08-28	util: volteer/dedede: move generic SPDs to common location	Nick Vaccaro
2020-08-26	soc/intel/tigerlake: Rename pch_init() code	Alexey Buyanov
2020-08-25	util: Add spd_tools to generate DDR4 SPDs for TGL boards	Nick Vaccaro
2020-08-24	soc/intel/tigerlake: Fix IPU and Vtd config	Ravi Sarawadi
2020-08-21	soc/intel/tigerlake: Enable long cr50 ready pulses	Jes Klinke
2020-08-18	elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE	Aaron Durbin
2020-08-18	src: Remove unneded whitespace before tab	Elyes HAOUAS
2020-08-17	soc/intel/tigerlake: Allow fine grained control of S0iX states	Jes Klinke
2020-08-14	soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 5KB	Ravi Sarawadi
2020-08-12	soc/intel/tigerlake: Add IRQs for LPSS uart	Patrick Rudolph
2020-08-09	soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming	Aamir Bohra
2020-08-07	soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE	Subrata Banik
2020-08-06	soc/intel/tigerlake: add common routine for DDR init	Nick Vaccaro
2020-08-05	{nb,soc}/intel: Use get_current_microcode_rev() for ucode version	Subrata Banik
2020-08-03	soc/intel/tigerlake: Invoke PCIe root port swapping	Caveh Jalali
2020-08-01	soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated	Subrata Banik
2020-07-29	soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold	John Zhao
2020-07-29	soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dB	Duncan Laurie
2020-07-28	soc/intel/tigerlake: Simplify is-device-enabled checks	Felix Singer
2020-07-26	soc/intel/tigerlake: Disable CPU PCIe in FSP	Shaunak Saha
2020-07-26	soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform	John Zhao
2020-07-26	src/soc/intel: Add include <types.h>	Elyes HAOUAS
2020-07-26	src: Update bare access to BOOL CONFIG_ vals to CONFIG()	Martin Roth
2020-07-26	cpu,soc/intel: Drop select SMP	Kyösti Mälkki
2020-07-26	src: Remove unused 'include <cbmem.h>'	Elyes HAOUAS
2020-07-26	src: Remove extra lines in license header	Elyes HAOUAS