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2020-06-30tigerlake: enable tcc_offset functionalitySumeet R Pawnikar
This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset to new value in devicetree. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I36b0d6aad4be8a9cbb145dcd66d65235d3f6ac35 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu
Add CpuReplacementCheck to chip options to control UPD FSPM SkipCpuReplacementCheck from devicetree. This UPD allows platforms with soldered down SoC to skip CPU replacement check to avoid a forced MRC traning. TEST=boot and verified with volteer Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. Found-by: Coverity CID 1429981 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iea3801585e8c294fb889a8137b534bb932696025 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42836 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_opsWilliam Wei
pmc_set_acpi_mode() should run after Chrome EC dealt with all host event bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test will fail). BUG=b:153249055 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Change the GBB flag to 0x140 then check SMI mask during depthcharge phase, make sure it's 0x0000000000000001. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
Not all FSPs based on FSP 2.1 supports the feature of external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE. Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is selected. Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake). Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-24soc/intel/tigerlake: Fix unresolved symbol CDW1 errorJohn Zhao
The dmesg shows unresolved symbol CDW1 with AE_NOT_FOUND error after booting to kernel. Fix the error by properly creating the buffer field CDW1 to cover all errors scenarios. BUG=b:140645231 TEST=Verified no AE_NOT_FOUND error related to \_SB.OSC.CDW1. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42693 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree. BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available for TGL-U. They are dependent upon the SKU of the CPU that the mainboard is running on. Volteer is updated here to use these new limits. To accomplish this, the SoC chip config's power_limits_config member was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE macros. Just before power limits are applied, the correct set of them is chosen from the array based on System Agent PCI ID. Therefore, a TGL board should have two sets of power limits available in the devicetree. BUG=b:152639350 TEST=On a Volteer SKU4 (4-core), verified the following console output: CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-22soc/intel/tigerlake: Update platform.asl to ASL2.0 syntaxV Sowmya
This change updates platform.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for volteer. Change-Id: I248f5e9a1e3ba4f6426167f0406073252cc6513a Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42506 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19soc/intel/tigerlake: Update TCSS for SW CM supportJohn Zhao
This change adds support for SW CM. Add Operating System Capabilities (_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet Protocol tunneling and enable PCIe tunneling as well. Remove Connect Topology(CNTP) command because kernel driver directly works with SW CM Thunderbolt firmware. Update _DSD method for USB4 support across XHCI and PCIe root ports. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-19tigerlake: add unique acpi device ids for dptfSumeet R Pawnikar
Add unique new acpi device ids for dptf for Tiger Lake soc based platforms and update volteer speficic dsdt.asl file accordingly. The Linux kernel driver expects these new acpi device ids for dptf functionalities. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18soc/intel/tigerlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZ4 compression technique to compress FSP-S. This provides some SPI ROM space savings (~36 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZ4 is chosen over LZMA since the decompression saves ~25 ms for an extra overhead of ~1KiB. LZ4 Compression: fsps.bin 0xe6fc0 fsp 254262 LZ4 (290816 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 712,361 (1,072) 18:finished LZ4 decompress (ignore for x86) 750,695 (38,334) LZMA Compression: fsps.bin 0xe6fc0 fsp 253415 LZMA (290816 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 707,696 (1,150) 16:finished LZMA decompress (ignore for x86) 767,763 (60,067) BUG=b:158034451 TEST=Build and boot volteer mainboard. Change-Id: I91e33eb7b688b5383f3a0075a28ac21250314973 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42444 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim
This patch adds support for enabling/disabling PCIe hot-plug via a chip config option PcieRpHotPlug, which is copied to the corresponding FSP-S UPD. BUG=b:156879564 BRANCH=none TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
Attempts to write to APM_CNT IO port should always be guarded with a test to verify SMI handler has been installed. Immediate followup removes redundant HAVE_SMI_HANDLER tests. Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/intel/tigerlake: enable CPU_INTEL_COMMONAlex Levin
Since we plan to use VMX, enable CPU_INTEL_COMMON. BUG=b:157388365 TEST=tested on Volteer Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: I5e7bdb4310947dd8a94ee554834a67ce94377ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-12soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda
For Tiger Lake platforms, this patch set provides a way to override PCH external VR settings and ext rail voltage/current through devicetree. This enables setting of optimal settings for FIVRs for a particular PCH type. BUG=None BRANCH=None TEST=Build and boot volteer. Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ic55472d392f27d153656afbe8692be7e243bb374 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41424 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10soc/intel/tigerlake: Add Hot-Plug and PME event handlers for ThunderboltJohn Zhao
This change adds Hot-Plug and power management event handers(_L61 & _L69) respectively for Thunderbolt in the GPE scope. The _L61 method invokes sub-method HPEV to support Hot-Plug wake event from Thunderbolt PCIe root ports. This method intercepts Presence Detect Changed interrupt and make sure the L0s is disabled on empty slots. The _L69 method checks and clears root port's PME SCI status. BUG=b:156435065 TEST=Verified multiple hot plug successfully with Lenovo dock. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-10ACPI: Remove Kconfig COMMON_FADTKyösti Mälkki
Also remove default mb/*/fadt.c from Makefiles. Change-Id: I6a2839c524f8311ec9a382a84066afc7d579eaca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41948 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao
The Connect Topology Command(CNTP) is sent with default timeout value (0x1388) along with FW CM. The CNTP is supposed to be skipped while using SW CM. While transition from FW CM to SW CM, the default timeout value could cause boot time delay up to ~10 seconds. Set this FSPS UPD ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs value. While FSP finds this UPD value being 0, FSP will skip sending CNTP. BUG=b:155893566 TEST=Built image with SW CM Thunderbolt firmware and verified no outstanding delay time while using FSP v3197 during boot to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42056 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09soc/intel/tigerlake: Increase heap sizeDuncan Laurie
With SoundWire and USB4 enabled some boards are running out of memory with all of the ACPI devices and properties. Increase the heap size to accommodate. BUG=b:147462631 TEST=Successfully boot on volteer SKU5 board with SoundWire enabled, before boot was failing with "Error! memalign: Out of memory" Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I0245bdfad93b381871514578e66640e7fe6fa5c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-08spd/lp4x: Set manufacturer part name to blank (0x20)Furquan Shaikh
As per JEDEC spec, manufacturer part name should be set to blank (0x20). This change updates gen_spd.go to set bytes 329-348 as 0x20 and regenerates SPDs for TGL and JSL. Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda
This change updates gpio_op.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for Volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib54b3f7da828ce8d232fcea0639077970638f610 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-06soc/intel/tigerlake: Add CPU ID for TGL B0Jamie Ryu
Reference: - TGL User Guide #613584 Rev 2.2 - TGL User Guide #605534 Rev 1.0 BRANCH=none BUG=none TEST=build and boot tglrvp Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41516 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06lp4x: Add new memory parts and generate SPDsFurquan Shaikh
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.goFurquan Shaikh
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with TGL-based mainboards. Following files are added: 1. spd-*.hex: SPD files auto-generated by gen_spd.go 2. spd_manifest.generated.txt: Manifest file auto-generated by gen_spd.go Mainboards can use the SPD files from SoC directly when creating SPD binary to add to CBFS. BUG=b:147321551,b:155239397 Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-06-03soc/tigerlake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-03soc/intel/tigerlake: update elog to include CSME reset causesderek.huang
Call out the CSME-initiated bits from HPR_CAUSE0 register and update the elog to include reset causes Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14 Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-02soc/intel/common/{pch,sata}: Remove SATA common code driverSubrata Banik
Right now all FSP2.0 based IA platform doesn't need this driver anymore hence removing to avoid debug and maintenance effort. TEST=Verified booting from SATA on SPT/CNP/ICP/TGP PCH platforms. Change-Id: Ied3832b26ba1fdd4c30fafe8149689a01d302c3e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41674 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02{icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includesElyes HAOUAS
Drop unused includes and add missing <intelblocks/systemagent.h>. Change-Id: I06c8b2bf65283c3c1fcd25fdaae298b82fc0e09c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-31soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda
This change updates pch_hda.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for Volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ia2bab6dcbac9eae76ac4258c44bb19425c8b5c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-31soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0Venkata Krishna Nimmagadda
This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-30soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao
Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA controllers setting. BUG=:b:146624360 TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling. lspci shows TcssDma0(0d.2) and TcssDma1(0d.3). Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Implement soc_get_pmc_mux_device()Tim Wawrzynczak
The ChromeOS EC is adding new entries to its USBC.CONx devices (see later patch), and it needs to get access to the PMC.MUX device so that its ACPI path can be retrieved. This provides a weak function to return NULL for all Intel SoCs except for Tiger Lake, which locates the device if it is found in the devicetree. Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Generate PMC ACPI device at runtimeTim Wawrzynczak
In an attempt to help reduce the amount of static ASL files that are littered throughout the codebase, pmc.asl was converted to runtime SSDT generation instead. If future SoCs reuse the same PMC, then this function can be moved to soc/intel/common/block/pmc for example. TEST=Verified the following was in the decompiled SSDT: Scope (\_SB.PCI0) { Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Tiger Lake IPC Controller") Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xFE000000, // Address Base 0x00010000, // Address Length ) }) } } Also the following found in linux's /var/log/messages: "acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC ACPI device was found and its _CRS was locatable. Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/41408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28soc/intel/tigerlake: Configure THCWonkyu Kim
Enable/Disable THCx though devicetree BUG=None BRANCH=None TEST=Boot and check FSP log for THC setting Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If7683969161be67f68f441c28c80503de39079b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Correct GPIO community PID configurationEric Lai
Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify PCR port id is correct for each community. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5dc48e5b31f43853b3a613c17f13f7df71f1fbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41725 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/common: Improve Type16 SMBIOS tablesPatrick Rudolph
Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-05-27soc/intel/gma: Implement fsp_soc_get_igd_bar() in common codeNico Huber
`fsp/util.h` draws incompatible UDK headers in. Hence, we have to declare it locally again. Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/intel/gma: Move display and opregion init to common codeNico Huber
Change-Id: I359b529df44db7d63c5a7922cb1ebd8e130d0c43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40725 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27drivers/intel/gma: Move IGD OpRegion to CBMEMNico Huber
It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and intel_backlight + acpi_video synchronize, both before and after suspend. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Remove MIPI clock setting from devicetreeSrinidhi N Kaushik
In Tiger Lake we have support for enabling MIPI clocks at runtime in ACPI. Hence remove setting pch_islclk from devcietree and chip.h. Also update functions which reference pch_isclk. BUG=b:148884060 Branch=None Test=build and boot volteer and verify camera functionality Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Delete unused configurationWonkyu Kim
Delete below configuration - Heci3Enabled: deprecated, see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442 - PchIshEnable: don't need as it's handled by devicetree dev on/off, see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87 BUG:b:151166877 BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26soc/intel/tigerlake: Disable VMDWonkyu Kim
It's already disabled by FSP default but disable VMD by devicetree to remove dependency with FSP default setting. BUG=None Branch=None Test=Build TGLRVP and boot up and check FSP log for checking VMD is disabled. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnableJohn Zhao
This adds FSP UPD D3HotEnable and D3ColdEnable for configuration. D3Hot low power mode support is for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers. D3Cold is lower mode for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold transition. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I6782cde6a1bfe13f46e75db8c85537c6d62f5d41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-26soc/intel/tigerlake: Fix wrong operation region for CPU to PCH methodJohn Zhao
CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation region to be SystemIO and ACPI_BASE_ADDRESS. BUG=b:156530805 TEST=Built and booted to kernel. Signed-off-by: John zhao <john.zhao@intel.com> Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-14 04:14:16 +0000