index
:
coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
vimacs
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
tigerlake
Age
Commit message (
Expand
)
Author
2021-05-07
soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
Kane Chen
2021-05-06
soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
Tim Wawrzynczak
2021-05-06
soc/intel/tigkerlake: Add IOM PCR PID
Tim Wawrzynczak
2021-05-06
soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities
Tim Wawrzynczak
2021-05-06
soc/intel/tigerlake: Add known GPIO virtual wire information
Tim Wawrzynczak
2021-05-03
soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros
Tim Wawrzynczak
2021-05-03
device: Switch pci_dev_is_wake_source to take pci_devfn_t
Tim Wawrzynczak
2021-04-26
soc/intel/tigerlake: Use device ID from pci_devs header file
John Zhao
2021-04-21
soc/intel: Replace open-coded buffer length calculation
Angel Pons
2021-04-21
soc/intel: Fix typo in comment
Angel Pons
2021-04-21
soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC
Rizwan Qureshi
2021-04-21
soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure
John Zhao
2021-04-13
dptf: Move platform-specific information to `struct dptf_platform_info`
Tim Wawrzynczak
2021-04-06
intel/tigerlake: Add Acoustic features
Shaunak Saha
2021-03-28
soc/intel/tigerlake: Fix REG_BASE_SIZE
Tim Wawrzynczak
2021-03-28
soc/intel/tigerlake: Move TCSS code to intel/common/block
Tim Wawrzynczak
2021-03-27
soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
Subrata Banik
2021-03-22
soc/intel/tigerlake: Add #include guards to soc/early_tcss.h
Tim Wawrzynczak
2021-03-22
util: Add DDR4 generic SPD for H4AAG165WB-BCWE
Nick Vaccaro
2021-03-19
soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable
Derek Huang
2021-03-15
soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device
Cliff Huang
2021-03-15
soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
Cliff Huang
2021-03-12
soc/intel/*: drop UART pad configuration from common code
Michael Niewöhner
2021-03-05
soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
Brandon Breitenstein
2021-03-05
soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and soc
Brandon Breitenstein
2021-03-05
soc/intel/tigerlake: Fix NULL being passed for response buffer
Furquan Shaikh
2021-03-03
soc/intel: Factor out common smmrelocate.c
Angel Pons
2021-03-03
soc/intel/tigerlake: Re-use existing define in CrashLog implementation
Francois Toguo
2021-03-03
soc/intel: Retype `CnviBtAudioOffload` devicetree option
Angel Pons
2021-03-01
soc/intel: Drop `bootblock_cpu_init()` function
Angel Pons
2021-03-01
soc/intel: Drop `romstage_pch_init()` function
Angel Pons
2021-03-01
soc/intel: Factor out common smbus.h
Angel Pons
2021-03-01
soc/intel: Factor out common gpe.h
Angel Pons
2021-03-01
soc/intel: Factor out identical acpigen GPIO helpers
Angel Pons
2021-03-01
soc/intel: Include gfx.asl from northbridge
Angel Pons
2021-02-24
soc/intel/*/smmrelocate.c: Sync includes
Angel Pons
2021-02-24
soc/intel/*/smmrelocate.c: Uniformize cosmetics
Angel Pons
2021-02-24
soc/intel/*/pmutil.c: Align cosmetics across platforms
Angel Pons
2021-02-24
soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore
Aamir Bohra
2021-02-23
soc/intel/tigerlake: Remove polling for Link Active Status at resume
John Zhao
2021-02-22
soc/intel/tigerlake: Enable end of post support in FSP
Nick Vaccaro
2021-02-22
soc/intel/tigerlake: Add CrashLog implementation for intel TGL
Francois Toguo
2021-02-16
vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMIC
Kyösti Mälkki
2021-02-16
ACPI: Add acpi_reset_gnvs_for_wake()
Kyösti Mälkki
2021-02-16
soc/intel: Drop aliases on MMCONF_BASE_ADDRESS
Kyösti Mälkki
2021-02-15
soc/intel: Remove unused <console/console.h>
Elyes HAOUAS
2021-02-11
src: Remove unused <arch/cpu.h>
Elyes HAOUAS
2021-02-10
soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
Shreesh Chhabbi
2021-02-09
soc/amd,intel: Drop s3_resume parameter on FSP-S functions
Kyösti Mälkki
2021-02-08
soc/intel: Drop CID1 from GNVS
Kyösti Mälkki
[next]