coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-12-14	src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL	Shreesh Chhabbi
2020-12-14	soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option	Shreesh Chhabbi
2020-12-14	soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage	Sridhar Siricilla
2020-12-14	soc/intel/tigerlake: Drop unreferenced devicetree settings	Angel Pons
2020-12-10	soc/intel/tigerlake: Check TBT & TCSS ports for wake events	Tim Wawrzynczak
2020-12-10	soc/intel/common: Adapt XHCI elog driver for reuse	Tim Wawrzynczak
2020-12-09	soc/intel/common/dmi: Move DMI defines into DMI driver header	Srinidhi N Kaushik
2020-12-09	soc/intel/tigerlake: Enable support for extended BIOS window	Furquan Shaikh
2020-12-08	src/soc/intel/tigerlake: Add SPI DMI Destination ID	Srinidhi N Kaushik
2020-11-30	soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices	Tim Wawrzynczak
2020-11-30	lp4x: Add new memory parts and generate SPDs	Nick Vaccaro
2020-11-29	soc/intel: Configure P2SB before other PCH controllers	Furquan Shaikh
2020-11-22	soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and ...	Bora Guvendik
2020-11-20	soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration	Duncan Laurie
2020-11-20	soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement	Duncan Laurie
2020-11-20	soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox	Duncan Laurie
2020-11-20	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	Michael Niewöhner
2020-11-16	lp4x: Add new memory parts and generate SPDs	David Wu
2020-11-13	soc/intel/tigerlake: Add code for early tcss	Brandon Breitenstein
2020-11-11	mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS	Shreesh Chhabbi
2020-11-11	soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode	Shreesh Chhabbi
2020-11-10	soc/intel/tigerlake: Log PM event from an internal device	Karthikeyan Ramasubramanian
2020-11-09	soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log	Tim Wawrzynczak
2020-11-09	soc/intel/tigerlake: Utilize vbt data size Kconfig option	Srinidhi N Kaushik
2020-11-09	soc/intel/*/chip: Remove unused devicetree entry	Patrick Rudolph
2020-11-05	soc/intel/tigerlake: Disable C1 C-state Demotion	Ravi Sarawadi
2020-11-03	soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix	Furquan Shaikh
2020-11-03	soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order	Subrata Banik
2020-11-02	soc/intel: Use of common reset code block	Subrata Banik
2020-11-02	mb, soc/intel: Reorganize CNVi device entries in devicetree	Furquan Shaikh
2020-11-02	soc/intel: Add a driver for CNVi WiFi/BT controllers	Furquan Shaikh
2020-10-30	soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases	Duncan Laurie
2020-10-30	soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointers	Tim Wawrzynczak
2020-10-28	soc/intel: deduplicate ACPI timer emulation	Michael Niewöhner
2020-10-26	mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`	Michael Niewöhner
2020-10-26	soc/intel: drop unneeded ISST configuration code	Michael Niewöhner
2020-10-26	src: Include <arch/io.h> when appropriate	Elyes HAOUAS
2020-10-24	{cpu,soc}/intel: deduplicate cpu code	Michael Niewöhner
2020-10-23	soc/intel/tigerlake: Add Acoustic features	Shaunak Saha
2020-10-21	soc/intel/common: Fix ACPI device name for USB4 DMA device	Duncan Laurie
2020-10-21	soc/intel: convert XTAL frequency constant to Kconfig	Michael Niewöhner
2020-10-21	soc/intel/common: add Kconfig for PM Timer emulation support	Michael Niewöhner
2020-10-19	soc/intel/*: drop useless XTAL shutdown qualification code	Michael Niewöhner
2020-10-19	soc/intel/tigerlake: Reflow long lines	Sridhar Siricilla
2020-10-17	cpu/intel,soc/intel: drop Kconfig for hyperthreading	Michael Niewöhner
2020-10-14	soc/intel/tigerlake: Enable and use USB4 PCIe driver	Duncan Laurie
2020-10-13	mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devices	Furquan Shaikh
2020-10-12	util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC	Nick Vaccaro
2020-10-09	soc/intel/tigerlake: Add chipset devicetree	Duncan Laurie
2020-10-08	soc/intel: Make use of common gfx.asl	Subrata Banik