coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-12	soc/intel/tigerlake: Add devicetree support to change PCH VR settings	Venkata Krishna Nimmagadda
2020-06-10	soc/intel/tigerlake: Add Hot-Plug and PME event handlers for Thunderbolt	John Zhao
2020-06-10	ACPI: Remove Kconfig COMMON_FADT	Kyösti Mälkki
2020-06-09	soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs	John Zhao
2020-06-09	soc/intel/tigerlake: Increase heap size	Duncan Laurie
2020-06-08	spd/lp4x: Set manufacturer part name to blank (0x20)	Furquan Shaikh
2020-06-07	soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntax	Venkata Krishna Nimmagadda
2020-06-06	soc/intel/tigerlake: Add CPU ID for TGL B0	Jamie Ryu
2020-06-06	lp4x: Add new memory parts and generate SPDs	Furquan Shaikh
2020-06-06	soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.go	Furquan Shaikh
2020-06-03	soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-06-03	soc/intel/tigerlake: update elog to include CSME reset causes	derek.huang
2020-06-02	soc/intel/common/{pch,sata}: Remove SATA common code driver	Subrata Banik
2020-06-02	src: Remove unused 'include <bootstate.h>'	Elyes HAOUAS
2020-06-02	{icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includes	Elyes HAOUAS
2020-06-02	src: Remove unused '#include <cpu/x86/lapic.h>'	Elyes HAOUAS
2020-05-31	soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntax	Venkata Krishna Nimmagadda
2020-05-31	soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0	Venkata Krishna Nimmagadda
2020-05-30	soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En	John Zhao
2020-05-28	soc/intel/tigerlake: Implement soc_get_pmc_mux_device()	Tim Wawrzynczak
2020-05-28	soc/intel/tigerlake: Generate PMC ACPI device at runtime	Tim Wawrzynczak
2020-05-28	soc/intel/tigerlake: Configure THC	Wonkyu Kim
2020-05-28	soc/intel/tigerlake: Correct GPIO community PID configuration	Eric Lai
2020-05-28	soc/intel/common: Improve Type16 SMBIOS tables	Patrick Rudolph
2020-05-27	soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code	Nico Huber
2020-05-27	soc/intel/gma: Move display and opregion init to common code	Nico Huber
2020-05-27	drivers/intel/gma: Move IGD OpRegion to CBMEM	Nico Huber
2020-05-26	soc/intel/tigerlake: Remove MIPI clock setting from devicetree	Srinidhi N Kaushik
2020-05-26	soc/intel/tigerlake: Delete unused configuration	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Disable VMD	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable	John Zhao
2020-05-26	soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method	John Zhao
2020-05-23	soc/intel/{jsl,tgl}: Override PRERAM_CBMEM_CONSOLE_SIZE default value	Subrata Banik
2020-05-22	soc/intel/tigerlake: Provide SoundWire controller properties	Duncan Laurie
2020-05-22	soc/intel/tigerlake: Add definition for PMC EPOC	Duncan Laurie
2020-05-20	tigerlake: enable DPTF functionality for volteer	Sumeet R Pawnikar
2020-05-20	soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()	Duncan Laurie
2020-05-20	soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutil	Tim Wawrzynczak
2020-05-20	soc/intel/tigerlake: Move PMC PCI resources under PMC device	Tim Wawrzynczak
2020-05-20	tigerlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-20	soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg	Brandon Breitenstein
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-18	soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override	Eric Lai
2020-05-18	soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method	John Zhao
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh
2020-05-12	soc/intel/tigerlake: Correct IRQ interrupt	Wonkyu Kim
2020-05-12	device/pci_device: Extract pci_domain_set_resources from SOC	Raul E Rangel
2020-05-12	soc/intel/tigerlake: Control SATA and DMI power optimization	Shaunak Saha