| Age | Commit message (Expand) | Author |
|---|
| 2020-09-08 | soc/intel/tigerlake: Skip GPIO configuration from FSP | Srinidhi N Kaushik |
| 2020-09-08 | soc/intel/tigerlake: Add SMRR Locking support | Tim Wawrzynczak |
| 2020-09-06 | soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default | Michael Niewöhner |
| 2020-09-04 | soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_CO... | Elyes HAOUAS |
| 2020-09-04 | soc/intel/tigerlake: Remove unused PID_SDX macro | Subrata Banik |
| 2020-09-02 | soc/intel/tigerlake: Add mainboard hook for overriding SoC config | Jes Klinke |
| 2020-08-28 | soc/intel/tigerlake: add ddr4-spd-empty.hex | Aaron Durbin |
| 2020-08-28 | util: Add memory parts needed by zork boards | Rob Barnes |
| 2020-08-28 | util/gen_spd: translate DeviceBusWidth to die bus width | Nick Vaccaro |
| 2020-08-28 | util: rename lp4x spds to include "lp4x-" in name | Nick Vaccaro |
| 2020-08-28 | util: volteer/dedede: move generic SPDs to common location | Nick Vaccaro |
| 2020-08-26 | soc/intel/tigerlake: Rename pch_init() code | Alexey Buyanov |
| 2020-08-25 | util: Add spd_tools to generate DDR4 SPDs for TGL boards | Nick Vaccaro |
| 2020-08-24 | soc/intel/tigerlake: Fix IPU and Vtd config | Ravi Sarawadi |
| 2020-08-21 | soc/intel/tigerlake: Enable long cr50 ready pulses | Jes Klinke |
| 2020-08-18 | elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE | Aaron Durbin |
| 2020-08-18 | src: Remove unneded whitespace before tab | Elyes HAOUAS |
| 2020-08-17 | soc/intel/tigerlake: Allow fine grained control of S0iX states | Jes Klinke |
| 2020-08-14 | soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 5KB | Ravi Sarawadi |
| 2020-08-12 | soc/intel/tigerlake: Add IRQs for LPSS uart | Patrick Rudolph |
| 2020-08-09 | soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming | Aamir Bohra |
| 2020-08-07 | soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE | Subrata Banik |
| 2020-08-06 | soc/intel/tigerlake: add common routine for DDR init | Nick Vaccaro |
| 2020-08-05 | {nb,soc}/intel: Use get_current_microcode_rev() for ucode version | Subrata Banik |
| 2020-08-03 | soc/intel/tigerlake: Invoke PCIe root port swapping | Caveh Jalali |
| 2020-08-01 | soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated | Subrata Banik |
| 2020-07-29 | soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold | John Zhao |
| 2020-07-29 | soc/intel/tigerlake: Set default USB3 de-emphasis to -3.5dB | Duncan Laurie |
| 2020-07-28 | soc/intel/tigerlake: Simplify is-device-enabled checks | Felix Singer |
| 2020-07-26 | soc/intel/tigerlake: Disable CPU PCIe in FSP | Shaunak Saha |
| 2020-07-26 | soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform | John Zhao |
| 2020-07-26 | src/soc/intel: Add include <types.h> | Elyes HAOUAS |
| 2020-07-26 | src: Update bare access to BOOL CONFIG_ vals to CONFIG() | Martin Roth |
| 2020-07-26 | cpu,soc/intel: Drop select SMP | Kyösti Mälkki |
| 2020-07-26 | src: Remove unused 'include <cbmem.h>' | Elyes HAOUAS |
| 2020-07-26 | src: Remove extra lines in license header | Elyes HAOUAS |
| 2020-07-25 | soc/intel/tigerlake: Update Pkg C-State latencies | Ravi Sarawadi |
| 2020-07-25 | soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU | Sumeet R Pawnikar |
| 2020-07-25 | soc/intel/tigerlake: Update Tiger Lake SA IDs | Derek Huang |
| 2020-07-21 | soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2 | Subrata Banik |
| 2020-07-21 | src: Use ACPI macros | Elyes HAOUAS |
| 2020-07-15 | soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs | Shaunak Saha |
| 2020-07-14 | src: Remove unused 'include <stdint.h> | Elyes HAOUAS |
| 2020-07-12 | soc/intel/tigerlake: Move tco_configure to bootblock | Tim Wawrzynczak |
| 2020-07-12 | soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) device | John Zhao |
| 2020-07-12 | soc/intel/tigerlake: Add Type-C IOM base address and size macro | John Zhao |
| 2020-07-12 | soc/intel/tigerlake: Add new IGD device | Ravi Sarawadi |
| 2020-07-09 | mainboard/intel/tglrvp: Remove unused PrmrrSize chip config | Subrata Banik |
| 2020-07-07 | soc/intel/common/block: Add new block DTT | Tim Wawrzynczak |
| 2020-07-07 | soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master | John Zhao |
