coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-02-08	soc/intel/{baytrail,broadwell}: Add missing <cbmem.h>	Angel Pons
2021-02-08	soc/intel/braswell,skylake: Drop logo parameters from devicetree	Kyösti Mälkki
2021-02-08	soc/intel: Drop CID1 from GNVS	Kyösti Mälkki
2021-02-07	soc/intel/broadwell/include/soc/me.h: Clean includes	Elyes HAOUAS
2021-02-07	soc/intel/quark/storage_test.c: Remove redundant <commonlib/cbmem_id.h>	Elyes HAOUAS
2021-02-07	acpi: Fix BERT size_t printf format error	Benjamin Doron
2021-02-07	soc/intel/alderlake: Increase VBT size to 9 KiB	Maulik V Vaghela
2021-02-07	soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors	Angel Pons
2021-02-07	soc/intel/broadwell: Convert to ASL 2.0 syntax	Elyes HAOUAS
2021-02-06	drivers/intel/fsp2_0: Add support for MP services2 PPI	Aamir Bohra
2021-02-06	intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI	Furquan Shaikh
2021-02-06	intel: Drop FSP_PEIM_TO_PEIM_INTERFACE	Furquan Shaikh
2021-02-06	soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAY	Kyösti Mälkki
2021-02-06	sb,soc/intel: Add wake source fields in GNVS	Kyösti Mälkki
2021-02-05	soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor	Kyösti Mälkki
2021-02-05	soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed	Tim Chu
2021-02-05	soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment	Elyes HAOUAS
2021-02-05	soc/intel/alderlake: Refactor PCIE port config	Eric Lai
2021-02-05	soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write	Angel Pons
2021-02-04	drivers/intel/fsp2_0: Fix running on x86_64	Patrick Rudolph
2021-02-04	acpi: Add support for reporting CrashLog in BERT table	Francois Toguo
2021-02-04	soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0	John Zhao
2021-02-04	src: Remove unused <bootstate.h>	Elyes HAOUAS
2021-02-03	soc/intel/tgl: Add configurable value for ConfigTdpLevel	Derek Huang
2021-02-03	pci_ids/intel: Add missing CFL-S GT1 IGD IDs	Nico Huber
2021-02-03	pci_ids/intel: Correct 0x3e96, it's a CFL-S part	Nico Huber
2021-02-03	src: Remove unused <cbmem.h>	Elyes HAOUAS
2021-02-03	intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected	Johnny Lin
2021-02-03	soc/intel: Fix compilation on x86_64	Patrick Rudolph
2021-02-02	soc/intel/baytrail,braswell: Drop TOLM from GNVS	Kyösti Mälkki
2021-02-02	soc/intel/baytrail,braswell: Sync PCI memory region in ASL	Kyösti Mälkki
2021-02-01	soc/intel/broadwell/gma.c: Add missing `break` in switch	Angel Pons
2021-02-01	soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CAPABLE	Elyes HAOUAS
2021-02-01	src/soc/intel: Remove CPU_INTEL_COMMON_SMM selection	Elyes HAOUAS
2021-02-01	src: Remove unused <cpu/x86/smm.h>	Elyes HAOUAS
2021-02-01	soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ	Subrata Banik
2021-02-01	soc/intel/elkhartlake: Config PlatformDebugConsent	Frans Hendriks
2021-02-01	soc/intel/common/sata: Add support for Cannon Lake SATA (HALO)	Erik van den Bogaert
2021-02-01	soc/intel/broadwell/pch/sata.c: Don't enable Bus Master	Angel Pons
2021-02-01	soc/intel/*: Get rid of custom microcode caching	Patrick Rudolph
2021-02-01	soc/intel/xeon_sp: Use native CAR teardown	Arthur Heymans
2021-02-01	drivers/intel/fsp2_0: Use coreboot postcar with FSP-T	Arthur Heymans
2021-01-31	soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK	Michael Niewöhner
2021-01-30	soc/intel/broadwell/pch: Drop some `config_of` uses	Angel Pons
2021-01-30	soc/intel/broadwell: Move `ramstage.c` to PCH scope	Angel Pons
2021-01-30	soc/intel/broadwell: Make `broadwell_init_pre_device` static	Angel Pons
2021-01-30	soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig options	Angel Pons
2021-01-30	soc/intel/broadwell: Define and use MMCONF_BUS_NUMBER	Angel Pons
2021-01-30	soc/intel/broadwell: Use common SMBus code	Angel Pons
2021-01-30	soc/intel/{baytrail,broadwell} Fix building with refcode blobs	Angel Pons