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2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09drivers/intel: Move FSP stage_cache implementation into common blockSubrata Banik
Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.hSubrata Banik
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08intel/fsp_baytrail: Move TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-07soc/intel/icelake: Remove redundant gpio.c from Makefile.incSubrata Banik
Change-Id: Ibddc2363e9bfea9ae41e4807435acb2e788dcb93 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-07soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstageFurquan Shaikh
This change intentionally removes the definition of PCH_DEV_PMC from ramstage to avoid silent errors. This device gets hidden from PCI bus in FSP-S and hence dropped from the root bus by the resource allocator. In order to avoid incorrect references to the device, avoid defining it in ramstage where it known to return NULL. BUG=b:136861224 Change-Id: I4f69470ec80c7127a2b604ed2b1f794f5a63e126 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34120 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07soc/intel/icelake: Get rid of unused dev paramFurquan Shaikh
This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: I861bb132acf113c9d306175b670bf4a1ff742c28 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-07soc/intel/icelake: Use SA_DEV_ROOT instead of PCH_DEV_PMCFurquan Shaikh
PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets removed from the root bus as leftover unused device. With change 903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses of dev_find_slot() were replaced by pcidev_path_on_root() which relies on scanning of root bus to find the requested device. Since PMC device is removed from the root bus, pcidev_path_on_root() returns NULL for it thus resulting in configuration being skipped for the PMC ultimately resulting in S3 failures. Since the PCH_DEV_PMC was just used to get to chip config, this change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT. BUG=b:136861224 Change-Id: Id68db8382b7b98e8e2e4a65ded1a6fb3bd057051 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-07soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev paramFurquan Shaikh
This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-07soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMCFurquan Shaikh
PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets removed from the root bus as leftover unused device. With change 903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses of dev_find_slot() were replaced by pcidev_path_on_root() which relies on scanning of root bus to find the requested device. Since PMC device is removed from the root bus, pcidev_path_on_root() returns NULL for it thus resulting in configuration being skipped for the PMC ultimately resulting in S3 failures. Since the PCH_DEV_PMC was just used to get to chip config, this change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT. BUG=b:136861224 TEST=Verified that S3 works fine on hatch. Change-Id: Ie5ade00ac2aca697608f1bdea9764b71c26e2112 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-06soc/intel/icelake: Fix outb orderLijian Zhao
Similar to CB:33940, fix outb orders. Change-Id: I1d35235abc7e02e6058f07809b738635861cc9e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jackpot51@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-06soc/intel/cannonlake: Fix outb orderJeremy Soller
outb accepts a value followed by a port Change-Id: I6fe3961b4f8cb2454e3b2564c3eae6af06c9e69d Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33940 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-06soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default valueSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix *** Pre-CBMEM romstage console overflowed, log truncated! *** issue. TEST=Verified on Hatch CML platform. Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Spoorthi K Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-06soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE widthSubrata Banik
As per EDS Sata port implemented register is byte width (bits[3:0]) hence converting required DWORD based read/write to BYTE width read/write. TEST=Able to boot from SATA device on CML hatch. Change-Id: I545b823318bae461137d41a4490117eba7c87330 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-05soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-HJeremy Soller
Some of the values used for GPIO_CFG and MISCCFG were not correct, causing GPEs to not work correctly. This adjusts them according to the values found in the original ACPI tables for the System76 Gazelle. Unfortunately, the Intel documentation[1] mentioned below is also incorrect. I have mentioned this to Intel already. The source for the Intel CoffeeLake FSP also confirms these new numbers. This was tested on a System76 Gazelle (gaze14). The EC uses GPP_K3 for its GPE and GPP_K6 is used for the lid switch GPE. Both function correctly after applying this change. [1] Intel Document #572235: Intel ® 300 Series Chipset Families Platform Controller Hub External Design Specification (EDS) - Volume 2 of 2 Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-04soc/intel/common: Increase SMM_MODULE_STACK_SIZE to 0x800Kane Chen
While running the s0ix cycling test, we observed SMM Handler caused a stack overflow. This error happens during event log access. This change is to increase the SMM_MODULE_STACK size to 0x800 BUG=b:135551854 TEST=suspend_resume test pass 500+ cycles, originally issue happenes within 150 cycle Change-Id: Ib4686b4d2d4fc3976068779314f4ee15ef4a8ae2 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-04soc/intel: Replace uses of dev_find_slot()Kyösti Mälkki
To call dev_find_slot(0, xx) in romstage can produce invalid results since PCI bus enumeration has not been progressed yet. Replace this with method that relies on bus topology that walks the root bus only. Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-04Revert "soc/intel/skylake/romstage: Increase size of postcar stack"Kyösti Mälkki
This reverts commit f70cb8bf968af75669325104756464ce6f4b824b. It was merged prematurely with some vague argumentation in the commit message and not all issues of reviewers were addressed. Change-Id: Ia336f3499fb29976a6b80383ef8b0f3d552f5640 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-03soc/intel/skylake: Add Kabylake-R microcode update filesArthur Heymans
This also corrects some CPU naming in comments. Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34000 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02src: Use CRx_TYPE type for CRxElyes HAOUAS
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/intel/cannonlake: Add support to log XHCI wake eventsPaul Fagerburg
Enhance elog wake source information with more details about which USB port resulted in a wake from S3 or S0ix. BUG=b:123429132 BRANCH=none TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` Ensure /build/hatch/firmware/image-hatch.serial.bin has been built. Plug a keyboard into a USB port on the DUT. Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via servo). On the console, run ``powerd_dbus_suspend``. Wait for the DUT to enter low power mode. Verify low power mode by issuing the ``powerinfo`` command on the EC console (via servo). Expect to see ``power state 4 = S0ix``. Press a key on the USB keyboard. The DUT wakes up. On the console, run ``mosys eventlog list`` and look for the wake source. 156 | 2019-06-26 09:46:07 | S0ix Enter 157 | 2019-06-26 12:14:05 | S0ix Exit 158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0 159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109 Program image-hatch.serial.bin into the DUT using flashrom. Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list`` sequence. 12 | 2019-06-26 14:52:23 | S0ix Enter 13 | 2019-06-26 14:53:07 | S0ix Exit 14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3 15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109 Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-02soc/intel/icelake: Disable HDA based on devicetreeSubrata Banik
Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-01Use 3rdparty/intel-microcodeArthur Heymans
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel. This allows for some finegrained control where family+model span multiple targets. Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products. The following MCU are get a new revision: old: sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328 new: sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352 Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-28{soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KBElyes HAOUAS
Change-Id: Ie922832bc7641a44a53c0cda8d808579c66420b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-28soc/intel/cannonlake: fix use of legacy 8254 timerMatt DeVillier
FSP sets the use of the 8254 timer via the Enable8254ClockGating UPD, which defaults to enabled, overriding what is set by coreboot. Per the FSP integration guide, this UPD needs to be disabled when a legacy OS is booted (ie, when SeaBIOS is used as the payload). Add a Kconfig option to set the UPD properly based on payload selection, and remove the existing coreboot code in lpc.c since it is either ineffective or being overridden by FSP. Test: build/boot out-of-tree WHL board with both SeaBIOS and Tianocore, ensure 8254 timer usage set correctly for each. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-26soc/intel/cannonlake/Kconfig: Don't have all variants select ↵Arthur Heymans
SOC_INTEL_CANNONLAKE This allows to use Kconfig options to differentiate between SOC variants. Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33559 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-25soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTEPatrick Havelange
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-series/c3000-family-datasheet.html Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com> Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-24cbfstool: Drop update-fit optionPatrick Rudolph
The ifittool is used instead. Drop old code. Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-24Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADERSubrata Banik
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set to ENV_RAMSTAGE. This approach will help to add future optimization (rampayload) in coreboot flow if required. Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-21soc/intel: Provide SPD manufacturer ID and module type to SMBIOSDuncan Laurie
The DIMM manufacturing ID was not being initialized and so the DIMMs were not described in SMBIOS tables properly. The module type can also be provided, but the SMBIOS code expects SPD module type values from DDR2 so the DDR3/4 values are adjusted before sending to SMBIOS. BUG=b:134897498 BRANCH=sarien TEST=dump and compare with dmidecode BEFORE: Type: DDR4 Manufacturer: Unknown (0) Form Factor: Unknown AFTER: Type: DDR4 Manufacturer: Hynix/Hyundai Form Factor: SODIMM Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-21soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASEArthur Heymans
What it really means to do is to use different FSP headers. Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21cpu/x86/msr: Move IA32_MISC_ENABLE bits to common placeElyes HAOUAS
Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21soc/intel/skylake: Clean up KconfigArthur Heymans
This does the following: - select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1) - Remove stale Kconfig option on intel/saddlebrook - select SOC_INTEL_KABYLAKE on intel/kblrvp Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21soc/intel/skylake: Remove ROMCCFLAGSArthur Heymans
This is never used. Change-Id: I414acc38f72e206eb48cfd98214985c320862c91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21soc/intel/skylake/romstage: Increase size of postcar stackChristian Walter
I increase the size oof the postcar stack to prevent a stack overflow during the measured boot feature. After common string functions have been moved from inline into .c file (https://review.coreboot.org/c/coreboot/+/32901), I experienced a stack overflow in the postcar stage while verifiying the romstage during measured boot. To prevent this, the stack size should be increased. To play it safe, it should be increased to 8 KiB - though this is open for discussion. Change-Id: I6f1a4631bcadfb8c7d1de5bf0919e40990a65606 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-21soc/intel/common/block/pcr: Remove unneded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Vlado Cibic Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-20soc/intel/braswell/smbus.c: Add support for i2c mode block writeFrans Hendriks
Intel Braswell supports i2c block write using SMBus controller. smbus_i2c_block_write() is added to configure SMBus controller in i2c mode before calling do_i2c_block_write(). Add smbus.c to ramstage. BUG=N/A TEST=Verify LCD display is working on Facebook FBG-1701 Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-18soc/intel/skylake: Select microcode updates depending on discrete PCHArthur Heymans
Change-Id: I05e97484605306afc70c726187bda8091216c9cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-16soc/intel/common: Fix booting issue without default IGD enabledSubrata Banik
This patch ensures to boot platform without onboard GFX (PCI B0:D2:F0) enabled from mainboard devicetree.cb. TEST=Previously platform was dying at "GMADR is not programmed!" with IGD disabled. Change-Id: I8c907ee25db4538a84890f2ccc3187afa86604b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33449 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13soc/intel/{cml, whl}: Add option to skip HECI disable in SMMSubrata Banik
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13soc/intel/icelake: Replace PCI device LPC to ESPI as per EDSSubrata Banik
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2019-06-12vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155Aamir Bohra
This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-12{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK supportFrans Hendriks
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-09soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirementAamir Bohra
1. Gfx stolen memory requirement for ICL GFX 2. Enable PeiGraphicsPeim support Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31955 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLINGSubrata Banik
Skip GT specific programming in coreboot to support early parts without GT enable. Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33189 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/acpi: Remove Return for PS0/3Christian Walter
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements. Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/bootblock: Add SPT C236 to PCH TableChristian Walter
Add Skylake C236 to the PCH Table. The one which was already in there is actually the CM236 and not the C236. This can be checked in datasheet: 100-series-chipset-datasheet-vol-1 p. 25. Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-07soc/intel/cannonlake: Add _DSM method for SD controllerV Sowmya
The SD controller seems to take some time after restarting the clock at 1.8V before it actually switches from 3.3V to 1.8V. Add a _DSM method that simply sleeps when switching between 3.3V and 1.8V. Otherwise, the kernel times out too quickly waiting for the card to acknowledge the 1.8V switch. The card itself is waiting until it sees the clk signal being driven at 1.8V. BUG=b:125441242 TEST=Boot Hatch with SD card and CR2 removed, observe voltage switch succeeds. Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Signef-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 06:06:44 +0000