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path: root/src/soc/intel
AgeCommit message (Expand)Author
2014-12-05fsp_baytrail: Update function disable codeMartin Roth
2014-12-05fsp_baytrail: Kconfig update for Gold 3 FSPMartin Roth
2014-12-05fsp_baytrail: Update microcode for Gold 3 FSP releaseMartin Roth
2014-12-05FSP platform microcode: Update to remove Kconfig variableMartin Roth
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
2014-12-05fsp_baytrail: update printk to use FSP_INFO_LEVELMartin Roth
2014-12-05fsp_baytrail: update for UPD_DEVICE_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update for UPD_SPD_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_DEFAULT_CHECK macroMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-12-01Mark non-executable files non-executablePatrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
2014-11-24intel/fsp_baytrail: add new CPUID for Baytrail I step D0Herve ELter
2014-11-21intel/fsp_baytrail: add Gold3 FSP supportYork Yang
2014-11-20Replace includes of build.h with version.hKyösti Mälkki
2014-11-19broadwell: move to per-device ACPI.Vladimir Serbinenko
2014-11-19fsp_baytrail: Fix ACPI 'Object is not referenced' warningsMartin Roth
2014-11-19fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.hMartin Roth
2014-11-18baytrail: fix range checkPatrick Georgi
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
2014-10-22broadwell: Update Haswell and Broadwell E0 microcodeDuncan Laurie
2014-10-22broadwell: Update microcodeDuncan Laurie
2014-10-22broadwell: ACPI, romstage, and other updatesDuncan Laurie
2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
2014-10-22broadwell: add new intel SOCDuncan Laurie
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-14intel/fsp_baytrail: Add padding so device_nvs location matches ACPIScott Radcliffe
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
2014-10-14intel/fsp_baytrail: Clear the GNVS area prior to fillingScott Radcliffe
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