coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-07-09	soc/intel/baytrail/pmutil.c: Constify string arrays	Angel Pons
2020-07-09	soc/intel/baytrail/pmutil.c: Do not hardcode num_bits	Angel Pons
2020-07-09	soc/intel/baytrail: Align whitespace and comments	Angel Pons
2020-07-09	soc/intel/baytrail: Rename "pmc.h" to "pm.h"	Angel Pons
2020-07-09	mainboard/intel/tglrvp: Remove unused PrmrrSize chip config	Subrata Banik
2020-07-09	soc/intel/braswell: Drop some BIOS_SPEW printk's	Angel Pons
2020-07-09	soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND	Angel Pons
2020-07-07	soc/intel/common/block: Add new block DTT	Tim Wawrzynczak
2020-07-07	soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master	John Zhao
2020-07-07	soc/intel/{tiger,jasper}lake: Add IPU to soc_acpi_name	Tim Wawrzynczak
2020-07-07	soc/intel/common: Add a minimal PCI driver for IPU	Tim Wawrzynczak
2020-07-07	lp4x: Add new memory parts and generate SPDs	David Wu
2020-07-06	src/**/acpi/smbus.asl: Drop dead code	Angel Pons
2020-07-06	soc/intel: Drop unused `#include <reg_script.h>`	Angel Pons
2020-07-06	soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init	Maulik V Vaghela
2020-07-04	soc/intel/xeon_sp/cpx: update HOB display code	Jonathan Zhang
2020-07-04	soc/intel/xeon_sp: Add read CPU PPIN MSR function	Johnny Lin
2020-07-04	soc/intel/tigerlake: Remove unused EHL DID from TGL SoC	Subrata Banik
2020-07-03	soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot	Jamie Ryu
2020-07-03	drivers/intel/pmx_mux: Remove redundant declaration	Kyösti Mälkki
2020-07-03	soc/intel/common: Only touch Time Window Tau bits in supported SoCs	Tim Wawrzynczak
2020-07-01	soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry	Jamie Ryu
2020-07-01	soc/intel/cannonlake: make satahotplug user configurable via devicetree	Jonas Loeffelholz
2020-07-01	soc/intel/common/cpu: Don't set any TCC settings if offset is 0	Tim Wawrzynczak
2020-07-01	soc/intel/skylake: Update ASL syntax in xhci.asl	Edward O'Callaghan
2020-07-01	soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4	John Zhao
2020-07-01	ACPI GNVS: Replace uses of smm_get_gnvs()	Kyösti Mälkki
2020-06-30	soc/intel/cannonlake: Add UWES ASL into xhci.asl	Edward O'Callaghan
2020-06-30	jasperlake: enable tcc_offset functionality	Sumeet R Pawnikar
2020-06-30	tigerlake: enable tcc_offset functionality	Sumeet R Pawnikar
2020-06-30	ACPI: Drop typedef global_nvs_t	Kyösti Mälkki
2020-06-30	soc/intel/tigerlake: Add CpuReplacementCheck to chip options	Jamie Ryu
2020-06-30	soc/intel/tigerlake: Avoid NULL pointer dereference	John Zhao
2020-06-30	src: Remove whitespaces before tabs	Elyes HAOUAS
2020-06-29	soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_ops	William Wei
2020-06-28	vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt soc	Jonathan Zhang
2020-06-28	soc/intel/common: add TCC activation functionality	Sumeet R Pawnikar
2020-06-28	soc/xeon_sp/cpx: Define MSR PPIN related registers	Johnny Lin
2020-06-27	soc/intel/broadwell: Use common early SPI code	Angel Pons
2020-06-25	soc/intel/cannonlake: Add PchPmPwrCycDur to chip options	Sridhar Siricilla
2020-06-25	drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1	Jonathan Zhang
2020-06-25	soc/intel/xeon_sp: use edk2-stable202005 headers	Jonathan Zhang
2020-06-25	soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs	Jonathan Zhang
2020-06-25	soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define	Edward O'Callaghan
2020-06-24	soc/intel/tigerlake: Fix unresolved symbol CDW1 error	John Zhao
2020-06-24	soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register	Elyes HAOUAS
2020-06-24	src: Report byte-sized access for GPE0	Angel Pons
2020-06-24	ACPI: Replace smm_setup_structures()	Kyösti Mälkki
2020-06-24	ACPI: Replace uses of CBMEM_ID_ACPI_GNVS	Kyösti Mälkki
2020-06-22	soc/intel/tigerlake: Add CmdMirror option in chip.h	David Wu