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2019-12-093rdparts/fsp: Update fsp submoduleJohanna Schander
The name for the CoffeeLake FSP.fd was changed to Fsp.fd. Therefore the CoffeLake / WhiskeyLake default path was changed. Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09soc/intel/bsw/gpio: Factor out GPI macrosAngel Pons
This patch simplifies some GPIO macros by removing redundant code. Also, for the sake of completeness, add two missing macros. Change-Id: I838efe8b26f60d3e059f4ce18c116aefbc0b0400 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-06soc/intel/skylake: Add option to control microcode update inclusionWim Vervoorn
On embedded boards the cpu mounted on the board is known. So it is not required to include microcode for all possible Sky Lake and Kaby Lake cpus. This patch provides the possibility to only support the versions required. By default all microcode updates will be included and the versions not required can be removed using Kconfig. BUG=N/A TEST=build Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-05soc/intel/braswell: Use common sb code for SPI lockdown configurationArthur Heymans
This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-03src: Add missing include <stdlib.h>Elyes HAOUAS
Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-03soc/intel/cannonlake: Configure GPIO PM configuration in bootblockSubrata Banik
This patch performs below operations: 1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration 2. Move soc_gpio_pm_configuration() to gpio_common.c 3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration is updated with devicetree.cb value even with platform reset. BUG=b:144002424 TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-03soc/intel/common/cse: Update comment for post-CAR global worldPatrick Georgi
Change-Id: I4ec9d7d3af1c4d7713ec5dfe516b24d110303ff1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-02soc/intel/cannonlake: Add gfx.asl fileMathew King
Add gfx.asl file for cannonlake SOCs to allow for graphics-related ACPI devices and methods on cannonlake devices. BUG=b:142237145 TEST=gfx.asl added to drallion dsdt.asl Change-Id: I38a26f3135d571e2f9b63840d38fd4d3476fc142 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-12-02soc/intel: Intel graphics driver scans generic busMathew King
This change allows for Intel graphics devices to use drivers/generic/gfx driver to populate ACPI SSDT table for common graphics related devices and methods. BUG=b:142237145 TEST=On sarien_cml add generic/gfx to the devicetree and device is enumerated and correct SSDT ASL is observed. Change-Id: Ibc86a88687ac860ebef19a4b68af64fd50d12b8e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-02soc/intel/cannonlake: Fix compilationPraveen Hodagatta Pranesh
Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASEMaulik V Vaghela
since we support JSL and TGL soc under tigerlake folder, we need to make sure all soc related files get compiled based on CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake. We can control soc specific file compilation through Kconfig of individual soc. Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-12-02src/soc/intel: Add Cometlake-S and CMP-H skusGaggery Tsai
This patch adds some sku support for CML-S CPU and CMP-H chips. According to doc #605546: CML-S (6+2) G0: A0650h CML-S (6+2) G1: A0653h CML-S (10+2, 8+2) P0: A0651h CML-S (6+2, 10+2) Q0/P1: A0654h CMP-H HM470: 068Dh CMP-H WM490: 068Eh CMP-H QM480: 068Ch CMP-H H470: 0684h CMP-H Z490: 0685h CMP-H Q470: 0687h TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized Change-Id: I6bda09070ec330033eff95329448ace57e87144f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02src/: Remove g_ prefixes and _g suffixes from variablesPatrick Georgi
These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-29{northbridge,soc,southbridge}: Don't use both of _ADR and _HIDElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ifb777c09aeef09a6a4cbee254b081519f5b6c457 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-29soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This moves programming BAR's and setting up console in the bootblock. Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36873 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29soc/intel/braswell: Don't reinitialize SPI after lockdownArthur Heymans
With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: I9fae28185470f4d25ef1818627eb76ac38cf100b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36006 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29soc/intel/braswell: Use sb/intel/common/spi.cArthur Heymans
This common implementation is compatible. Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-28soc/intel/tigerlake: select correct chipset based on soc KconfigMaulik V Vaghela
Since we accomodate both Tigerlake and Jasperlake soc in single folder, we need to select IFD chipset correctly based on soc. Change-Id: I73cfe4f583da3a28c3b29d29a93ff62097130e27 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-11-28pci_ids: Update Intel Lewisburg SMBUS PCI IDJonathan Zhang
Change PCI_DEVICE_ID_INTEL_KBP_H_LWB_SMBUS to PCI_DEVICE_ID_INTEL_LWB_SMBUS. Ideally the abbreviation for Lewisburg should be LBG instead of LWB. However, LWB is used for consistency. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Anjaneya (Reddy) Chagam <anjaneya.chagam@intel.com> Change-Id: Ibc0cb6f2f7eb337180c2ae89015953a9aeaed68b Reviewed-on: https://review.coreboot.org/c/coreboot/+/37215 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28soc/intel/skl: Drop FSP_CAR remnantsNico Huber
FSP-T support was abandoned long ago for Skylake. With FSP1.1 support also dropped now, it's more visible that this code is unused. Change-Id: I83a9130ef403b498e2beea01749c178e547b0f08 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37251 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27soc/intel/skylake: Clean up report_cpu_info() functionUsha P
This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 2. Make fill_processor_name function available in bootblock. 3. Reuse fill_processor_name. TEST= Succesfully able to boot soraka and verify the cpu_name "CPU: Intel(R) Pentium(R) CPU 4415Y @ 1.60GHz" Change-Id: Idf7b04edc3fce147f7856591ce7e5a0cd05f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36840 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27soc/intel/cannonlake: Disable USB2 PHY Power gatingSurendranath Gurivireddy
Workaround to disable USB2 PHY power gating to fix issue seen when Apple 87W USB-C charger is connected in S0ix state on WHL platforms (based on Intel's recommendation). Issue is seen on CML platforms also. So, disable power gating for Drallion too. Add devicetree entry to set the flag to disable USB2 PHY power gating for different CNL PCH based platforms BUG=b:133775942 TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if the system wakes up after that Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com> Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27soc/intel/tigerlake: Fix smm_relocation_paramsKyösti Mälkki
Platform is not yet build-tested, this should have gone in with commit f5c0d61 intel/smm: Provide common smm_relocation_params. Change-Id: Iba667972e361d3ed463258357ab6bbde26ef1e06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-27soc/intel/baytrail: Don't reinitialize SPI after lockdownArthur Heymans
With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36008 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27soc/intel/baytrail: Use sb/intel/common/spi.cArthur Heymans
This common implementation is compatible. Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-27soc/skylake: Write the P2SB IBDF and HBDF registers in corebootAngel Pons
Do it in coreboot code instead of letting FSP do it. Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-26soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-TSubrata Banik
It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode update. The microcode update is loaded for all logical processors before reset vector. FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place hence skipping FSP-T loading ucode after CPU reset options. Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and CONFIG_CPU_MICROCODE_CBFS_LEN Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-26soc/intel/cannonlake: Add chip config to override CPU flex ratioSubrata Banik
This patch provides options to override descriptor default CPU flex ratio from coreboot code. cpu_ratio_override to provide the required CPU ratio. Note: Don't override the flex ratio if cpu_ratio is 0. BUG=b:142264107 TEST=Without override flex_ratio is 0 and verified booting to OS after overriding with flex_ratio value 5. Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-26sb/intel/common/spi: Add Baytrail/Braswell supportArthur Heymans
The mechanism for getting the SPIBAR is little different. Tested on Intel Minnowboard Turbot. Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-25soc/intel/tigerlake: Add Jasperlake soc KconfigMaulik V Vaghela
Add Kconfig option for Jasperlake soc and make tigerlake as a base soc. This will allow us to differentiate between soc features. Change-Id: Id5001dc498a7d7d5c7903dc3a3762da740fc9c8e Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-25soc/intel/broadwell: Fix 'dead increment'Elyes HAOUAS
Dead increment spotted out using clang-tools. Change-Id: Icfab0b9ce97722fe97a0306cb45fbc2bd072bad6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-22soc/intel/icelake: Make CpuMpPpi implementation default for ICLSubrata Banik
TEST=Could able to build and boot ICL DE system Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-22soc/intel/common/intelblocks: Define PAD_CFG0_MODE_NF7Nick Vaccaro
BUG=b:142961277 BRANCH=none TEST=none Change-Id: Ibe0991b2e0d13e07d65906201597f9021cfc7156 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-22soc/intel/skylake: Refactor pch_early_init() codeUsha P
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot soraka. Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-21Kconfig: Remove not found sourcesElyes HAOUAS
Change-Id: I3691a4162eecbd48321348e136f72b73da74e225 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37078 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21soc/intel/fsp_broadwell_de: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I8b6502b0894f9e2b8b1334871d7b6cde65cba7d4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-21soc/intel/fsp_baytrail: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-20soc/intel/skylake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Also fix the register offset in a comment in reset code. Tested successfully on X11SSM-F by reading ETR3. Change-Id: If190c3c66889ede105d958b423b38ebdcb698332 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/icelake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I3e450a473ccdf99221e82e0f857879039d78991b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36572 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/cannonlake: lockdown: lock global resetMichael Niewöhner
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20soc/intel/common: pmclib: make use of the new ETR address APIMichael Niewöhner
Make use of the new ETR address API in the ETR3 register related functions. Further, disabling and locking of global reset is now done at once to save one read-modify-write cycle, thus the function was renamed accordingly and the now redundant disabling in soc/apl got removed. Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20soc/intel/skylake: add soc implementation for ETR address APIMichael Niewöhner
Add soc implementation for the new ETR address API. Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-20cbfs: switch to region_device for location APIsAaron Durbin
Drop struct cbfs_props and replace with struct region_device object. The goal of the cbfs locator APIs are to determine the correct region device to find the cbfs files. Therefore, start directly using struct region_device in the cbfs location paths. Update the users of the API and leverage the default boot region device implementation for apollolake. Change-Id: I0158a095cc64c9900d8738f8ffd45ae4040575ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-18include: Make stdbool.h a separate fileJulius Werner
This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18*/Makefile: Always build enable_usbdebug.cArthur Heymans
This always builds the usb debug callback functions when implemented. They get garbage collected if CONFIG_USBDEBUG is not set. Change-Id: I33051df583645cd00d08e06774383763172d5822 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-16intel/skylake: Use new PCIe RP devicetree updateNico Huber
The old code stumbled when the whole first group of root ports was disabled and also made the (sometimes wrong) assumption that FSP would only hide function 0 if we explicitly told it to disable it. Change-Id: Ia6938ca6929c6d9d0293c4f0f0421e38bf53fb55 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36702 Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-16soc/intel: Implement PCIe RP devicetree update based on LCAPNico Huber
Most of the current implementations for FSP-based platforms make (sometimes wrong) assumptions how FSP reorders root ports and what is specified in the devicetree. We don't have to make assumptions though, and can read the root-port number from the PCIe link capapilities (LCAP) instead. This is also what we do in ASL code for years already. This new implementation acts solely on information read from the PCI config space. In a first round, we scan all possible DEVFNs and store which root port has that DEVFN now. Then, we walk through the devicetree that still only knows devices that were originally mentioned in `devicetree.cb`, update device paths and unlink vanished devices. To be most compatible, we work with the following constraints: o Use only standard PCI config registers. o Most notable, don't try to read the registers that configure the function numbers. FSP has undocumented ways to block access to non-standard registers. o Don't make assumptions what function is assigned to hidden devices. The following assumptions were made, though: o The absolute root-port numbering as documented in datasheets matches what is read from LCAP. o This numbering doesn't contain any gaps. o Original root-port function numbers below a PCI device start at function zero and also don't contain any gaps. Change-Id: Ib17d2b6fd34608603db3936d638bdf5acb46d717 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35985 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15soc/intel/skylake/acpi/dptf: Disable DTRP when no DPTF_TSRX_SENSOR_ID is definedWim Vervoorn
On mainboards without DPTF_TSRX_SENSOR_ID method DTRP is never called Only add the DTRP method when at least one sensor is enabled. BUG=N/A TEST=build Change-Id: I4fb26d5bbb7b334e759e7073b680f830f412467e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36856 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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