coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-26	soc/intel/xeon_sp: select UDK_2017_binding	Jonathan Zhang
2020-05-26	soc/intel/tigerlake: Remove MIPI clock setting from devicetree	Srinidhi N Kaushik
2020-05-26	soc/intel/tigerlake: Delete unused configuration	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Disable VMD	Wonkyu Kim
2020-05-26	apollolake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-26	soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable	John Zhao
2020-05-26	soc/intel/skylake/acpi/smbus.asl: Fix typo in comment	Elyes HAOUAS
2020-05-26	Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION	Kyösti Mälkki
2020-05-26	cannonlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-26	soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method	John Zhao
2020-05-26	soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options	Christian Walter
2020-05-26	intel/cannonlake: Implement PCIe RP devicetree update	Nico Huber
2020-05-26	soc/intel/jasperlake: correct IRQ routing Jasper Lake	Ronak Kanabar
2020-05-23	soc/intel/broadwell: Use SPDX identifier	Jacob Garber
2020-05-23	soc/intel/common/block: Update SA resource length to support 64 bit	Subrata Banik
2020-05-23	soc/intel/{jsl,tgl}: Override PRERAM_CBMEM_CONSOLE_SIZE default value	Subrata Banik
2020-05-22	soc/intel/tigerlake: Provide SoundWire controller properties	Duncan Laurie
2020-05-22	soc/intel/tigerlake: Add definition for PMC EPOC	Duncan Laurie
2020-05-21	soc/intel/tigerlake: Make audio devices scan the bus	Duncan Laurie
2020-05-20	tigerlake: enable DPTF functionality for volteer	Sumeet R Pawnikar
2020-05-20	soc/intel/tigerlake: Add TCSS devices to soc_acpi_name()	Duncan Laurie
2020-05-20	soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutil	Tim Wawrzynczak
2020-05-20	soc/intel/tigerlake: Move PMC PCI resources under PMC device	Tim Wawrzynczak
2020-05-20	tigerlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-20	icelake: remove unused processor power limits configuration	Sumeet R Pawnikar
2020-05-20	soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg	Brandon Breitenstein
2020-05-20	soc/intel/jasperlake: Add ACPI method to get GPIO PCR PID	Aamir Bohra
2020-05-20	soc/intel/common/acpi: Remove gpio community range	Aamir Bohra
2020-05-20	soc/intel/broadwell: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl	Furquan Shaikh
2020-05-20	soc/intel/broadwell: Update systemagent.asl to ASL2.0 syntax	Furquan Shaikh
2020-05-20	soc/intel/skylake: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl	Furquan Shaikh
2020-05-20	soc/intel/skylake: Update systemagent.asl to ASL2.0	Furquan Shaikh
2020-05-20	soc/intel/common/block/acpi: Fix error in shift operation for GPCL	Furquan Shaikh
2020-05-18	src: Remove unused 'include <string.h>'	Elyes HAOUAS
2020-05-18	src: Remove unused 'include <lib.h>'	Elyes HAOUAS
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-18	broadwell: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/jasperlake: Add function to display ME firmware status info	Krishna Prasad Bhat
2020-05-18	soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override	Eric Lai
2020-05-18	skylake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/common/block/smbus: Use i2c read eeprom to speedup SPD read	Wim Vervoorn
2020-05-18	jasperlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/common: add processor power limits control support	Sumeet R Pawnikar
2020-05-18	soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method	John Zhao
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-17	soc/intel/common: Rename cse_is_hfs3_fw_sku_custom()	Sridhar Siricilla
2020-05-17	soc/intel/common/block/acpi: Mask lower 20 bits of TOLUD	Furquan Shaikh
2020-05-17	soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax	Furquan Shaikh
2020-05-15	soc/intel: Correct comment on HMRFPO_ENABLE HECI command	Sridhar Siricilla
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh