coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-02-07	intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES	Barnali Sarkar
2018-02-07	soc/intel/skylake: Add Kabylake PCH H device ID's	V Sowmya
2018-02-06	soc/intel/skylake: sort CPU_SPECIFIC_OPTIONS and drop duplicate	Vadim Bendebury
2018-02-06	soc/intel/appololake: Remove dead MPINIT code selection	Arthur Heymans
2018-02-06	soc/intel/cannonlake: Increase heap size	John Zhao
2018-02-06	soc/intel/skylake: Add devicetree variable for PCIe HotPlug	Duncan Laurie
2018-02-06	soc/intel/skylake: Set PsysPmax value	Gaggery Tsai
2018-02-05	soc/intel/skylake: Set PsysPl3 and Pl4	Shelley Chen
2018-02-05	soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config space	Hannah Williams
2018-02-05	soc/intel/apollolake: Clear RTC failure bit after reading it	Furquan Shaikh
2018-01-31	soc/intel/skylake: Always add PM1_TMR block to FADT	Duncan Laurie
2018-01-31	soc/intel/skylake: Fix common timer frequency	Duncan Laurie
2018-01-31	soc/intel/cannonlake: CannonaLake make use of FVI information	Subrata Banik
2018-01-31	drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driver	Subrata Banik
2018-01-30	soc/intel/skylake: Add support for mode-aware DPTF	Furquan Shaikh
2018-01-30	drivers/spi: support cmd opcode deduction for spi_crop_chunk()	Aaron Durbin
2018-01-29	intel: Prepare registers so Windows drivers are happier	Patrick Georgi
2018-01-28	soc/intel/denverton_ns: Rename HARCUVAR macros to DENVERTON	Julien Viard de Galbert
2018-01-26	soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and report	Lijian Zhao
2018-01-26	soc/intel/apollolake: select NO_UART_ON_SUPERIO	Ravi Sarawadi
2018-01-25	drivers/i2c/designware: reduce API complication for bus config	Aaron Durbin
2018-01-25	soc/intel/skylake: Clean up the skylake PCH H device ID macros	V Sowmya
2018-01-25	soc/intel/cannonlake: enable pch link in bootblock	Caveh Jalali
2018-01-25	soc/intel/skylake: Send correct ddr_type to SMBIOS Table	Barnali Sarkar
2018-01-24	soc/intel/cannonlake: Add child CARD device into eMMC/SD controller	Subrata Banik
2018-01-24	soc/intel/cannonlake: Port SD Controller W/A from Intel Reference code	Subrata Banik
2018-01-24	soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference code	Subrata Banik
2018-01-24	drives/i2c/designware: incorporate device_operations support	Aaron Durbin
2018-01-24	drivers/i2c/designware: namespace soc functions	Aaron Durbin
2018-01-23	src/soc/intel/cannonlake: Update C-state latency control limits	Vaibhav Shankar
2018-01-23	mainboard/intel/cannonlake_rvp: Add support for MAX98373 speaker amp	N, Harshapriya
2018-01-23	mainboard/intel/cannonlake_rvp: Add support for SND_MAX98357_DA7219	Lijian Zhao
2018-01-23	soc/intel/cannonlake: Add audio NHLT support	Lijian Zhao
2018-01-18	security/tpm: Change TPM naming for different layers.	Philipp Deppenwiese
2018-01-18	security/tpm: Move tpm TSS and TSPI layer to security section	Philipp Deppenwiese
2018-01-17	soc/intel/cannonlake: Reserve PMC IO resources	Subrata Banik
2018-01-17	soc/intel/common: Add option to pass SoC IO resource	Subrata Banik
2018-01-17	soc/intel/apollolake/meminit_util_glk.c: Check for NULL	Ravi Sarawadi
2018-01-17	soc/intel/apollolake: Fix prev_sleep_state on G3 exit	Hannah Williams
2018-01-17	soc/intel/cannonlake: Add option to select FSP_CAR	Subrata Banik
2018-01-16	soc/intel/cannonlake: Program DMI PCR settings	Lijian Zhao
2018-01-16	soc/intel/apollolake: Set ACPI_FADT_LOW_PWR_IDLE_S0 for S0ix	Shaunak Saha
2018-01-15	Intel sch board & chip: Remove - using LATE_CBMEM_INIT	Martin Roth
2018-01-12	soc/intel/common/block: Check for NULL before dereference	Shaunak Saha
2018-01-12	soc/intel/skylake: Override KBL IccMax settings	Gaggery Tsai
2018-01-12	soc/intel/common: Add Intel HDA common block driver	Duncan Laurie
2018-01-10	soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock	Furquan Shaikh
2018-01-09	soc/intel/cannonlake: Remove redundent CNL CPUID macros	Subrata Banik
2018-01-08	soc/intel/cannonlake: Initialize DDI-A lane in Normal mode	Abhay Kumar
2018-01-07	soc/intel/cannonlake: provide LPDDR4 memory init	Nick Vaccaro