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2016-12-27cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier
Migrate duplicated enable_vmx() method from multiple CPUs to common folder. Add common virtualization option for CPUs which support it. Note that this changes the default to enable virtualization on CPUs that support it. Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-26soc/intel/skylake: set TCC activation by BSP onlySumeet Pawnikar
TCC activation functionality has package scope. It was set for all CPU in the system which is unnecessary. In this patch TCC activation is being set by the BSP only. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the TCC activation value before and after S3. Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17889 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23soc/intel/skylake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles successfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR InitBrenton Dong
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17063 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-15soc/intel/common: provide option to invalide MRC cache on recoveryAaron Durbin
Allow a board/platform to invalidate the normal MRC cache when hardware retraining is requested in recovery mode. A small 4 byte payload is used to update the latest data written. It will of course fail on MRC cache retreival on next usage. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17870 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15soc/intel/apollolake: don't probe flash manuallyAaron Durbin
Rely on boot_device_spi_flash() to provide the spi_flash object. There's no need to duplicate the probing logic. BUG=chrome-os-partner:56151 BRANCH=reef Change-Id: I91900a3dfad7ba92cbd3b0ace77b08db04cff0b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17867 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-14soc/intel/broadwell/lpc.c: don't zeroize existing gnvs tableMatt DeVillier
The gnvs table only needs to be zeroized after init; zeroizing an existing/populated table renders all I2C devices completely non-functional. TEST: boot Linux and observe all I2C devices functional Change-Id: Id149ad645dfe5ed999a65d10e786e17585abc477 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17828 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-13intel MMA: Enable MMA with FSP2.0Pratik Prajapati
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11x86 SMM: Fix use with RELOCATABLE_RAMSTAGEKyösti Mälkki
The value for _size was not evaluated correctly if ramstage is relocated, make the calculation runtime. While touching it, move symbol declarations to header file. Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08soc/intel/apollolake: Move privilege drop to later stageAndrey Petrov
Previously privilege drop was happening "too early" and that caused some PMC IPC programming (performed in FSP) to fail because sideband was already locked out. This change set moves privilege drop to later stage, after last FSP notify call. BRANCH=reef BUG=chrome-os-partner:60657 TEST=iotools rdmsr X 0x121, make sure they can't be read. Also dmesg|grep -i IPC to make sure there are no errors related Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17769 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08soc/intel/apollolake: Set PL2 in RAPL registerSumeet Pawnikar
This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/broadwell: set EM4/EM5 registers based on cdclkMatt DeVillier
The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17718 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07soc/intel/apollolake: Use the new SPI driver interfaceFurquan Shaikh
1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17562 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-07soc/intel/skylake: Remove unwanted spi_release callFurquan Shaikh
Skylake uses a special SPI Flash controller and does not require spi_claim_bus and spi_release_bus functionality. This was a leftover call from earlier cleanup, so remove it. Change-Id: Iea260813cf72b94b7e7c661dbe494a74351dc357 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17729 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/intel/skylake: Remove redundant BootLoaderTolumSize assignmentSubrata Banik
BootLoaderTolumSize FSP-M UPD is already initialized with cbmem_overhead_size() inside driver/fsp2_0/memory_init.c, hence remove the duplicate assignment. Change-Id: I0b1d9769cd2a863bf0547ce5f44928cacc5a63b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Drop redundant loggingKyösti Mälkki
Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17696 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06spi_flash: Make a deep copy of spi_slave structureFurquan Shaikh
Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-04spi_flash: Move spi flash opcodes to spi_flash.hFurquan Shaikh
BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I3b6656923bb312de470da43a23f66f350e1cebc7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17680 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02soc/intel/common: Add suppport for Extended VBTAbhay Kumar
With addition of new features in VBT its size got increased more than 6k and was unable to pass using mailbox 4 hence pass using mailbox 3 to kernel. BRANCH=none BUG=chrome-os-partner:60026 TEST=firmware screen and Chrome OS screen should come up. Change-Id: I359cf9bc402881161c9623cada689496716e04a5 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/17585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02soc/intel/apollolake: Drop privilege level to IA_UNTRUSTEDAndrey Petrov
As per guidelines CPU security level should be dropped before OS start, so that certain MSRs are locked out. Drop privilege levels on all logical CPUs. BUG=chrome-os-partner:60454 TEST=iotools rdmsr x 0x120, make sure bit 6 is set, rdmsr x 0x121 results in io error. Change-Id: I67540f6da16f58b822db9160d00b7a5e235188db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17665 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-02soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUsAndrey Petrov
Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-01lib/nhlt: add support for setting the oem_revisionAaron Durbin
In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: add helper to determine resume statusAaron Durbin
Instead of having callers query the romstage handoff resume status by inspecting the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17647 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30soc/intel/skylake: Pass proper CPU flex ratio override to FSPNaresh G Solanki
In bootblock, cpu flex ratio is set to non-turbo max. In FSP UPD, if CpuRatioOverride is zero, then it tries to program cpu ratio to zero. Since it is different than the non-zero value programmed in bootblock, FSP gives reset. To avoid the reset, set FSP UPD for CPU flex ratio override to that value as set in bootblock. Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17555 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Fix top_of_ram calculationNaresh G Solanki
FSP 2.0 implementation conditionally sets PMRR base based on EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being set since FSP 2.0 changed behavior from FSP 1.1 implementation. If prmrr base is non-zero value, then top_of_ram is prmrr base. If Probeless trace is enabled, then deduct trace memory size from calculated top_of_ram. Change-Id: I2633bf78705e36b241668a313d215d0455fba607 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Use SendVrMbxCmd1 for FSP 2.0Rizwan Qureshi
In FSP 2.0 the UPD to send extra VR Mailbox commands is switched from SendVrMbxCmd to SendVrMbxCmd1. Use the same in silicon initialization. Change-Id: I46bd50c9acc0456e2483f20ccb5e9ec2a0de232a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/17578 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/skylake: Move IO decode range out from pch_lpc_initTeo Boon Tiong
1. Move existing IO decode range from pch_lpc_init to early stage before SIO init. 2. At the same time, enable SIO decode range (0x2e/0x2f) for platform which use super IO. Change-Id: I72df16d0a784686d8cadfbee09b5aef60576ac43 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Remove pad configuration size hardcodingSubrata Banik
Existing GPIO driver inside coreboot use some hardcoded magic number to calculate gpio pad offset. Avoid this kind of hardcoding. Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Disable Legacy PME for Root portsNaresh G Solanki
Legacy PME are enabled by default in FSP UPD region. When Legacy PME is enabled, then an SCI is generated and should be handled by OS and BIOS/Coreboot in collboration. OS requires some ACPI methods (eg _L69) which help to determine the wake source and also to clear some registers. But this infrastructure is not present as of now in coreboot and also linux handles PMEs natively. Hence the SCI was never handled by OS and the status bits were never cleared i.e., PCI_EXP_STS. For this reason the level triggered SCI will remain active and the system will wake up as soon as it enters S3. To fix this, diabled Legacy PME (PmSci for Root ports). Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17553 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/apollolake: Add save/restore variable MRC cacheAndrey Petrov
Apollolake MRC cache is divided into two regions: constant and variable. Currently they are clubbed together. Since variable data changes across cold reboot it triggers invalidation of the whole cache region. This change declubs the data, adds routines to load/store variable data on flash. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I374519777abe9b9a1e6cceae5318decd405bb527 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17237 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/common: Add save/restore for variable MRC dataAndrey Petrov
Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30driver/intel/fsp2_0: Add version parameter to FSP platform callbackAndrey Petrov
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29intel/sch: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Forgot to actually "flip the bit" in commit ebc21d1 intel/sch: Switch to MMCONF_SUPPORT_DEFAULT Change-Id: Ic095594acb08bae17a6443bc302eb8bfb1ce2083 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17640 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28soc/intel/skylake: Add USB Port Over Current (OC) Pin programmingSubrata Banik
Program USB Overcurrent pins as per board schematics definition. BUG=none BRANCH=none TEST=Build and boot kunimitsu from USB device. Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-11-28soc/intel/skylake: Initialize UART based on CONFIG_UART_DEBUGTeo Boon Tiong
Current implementation checks for CONFIG_BOOTBLOCK_CONSOLE and then initializes UART. If only CONFIG_BOOTBLOCK_CONSOLE is enabled without enabling CONFIG_UART_DEBUG, there are compilation issues. This is the case when using SIO UART for Skylake DT platform. Hence initialize UART when CONFIG_UART_DEBUG is enabled and not based on CONFIG_BOOTBLOCK_CONSOLE. Also move BOOTBLOCK_CONSOLE out from UART_DEBUG to CPU_SPECIFIC_OPTIONS as part of the fix needed. Change-Id: Id422a55a68d64a06fc874bddca46b0ef5be6d596 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17349 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23soc/intel/skylake: Define early smbus functionsNaresh G Solanki
Define early smbus functions that can be used by mainboard to fetch spd. Change-Id: Id170b2b8e6fb3ebb147f37bf433a27d1162dc11c Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17433 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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