coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-28	soc/xeon_sp/cpx: Define MSR PPIN related registers	Johnny Lin
2020-06-27	soc/intel/broadwell: Use common early SPI code	Angel Pons
2020-06-25	soc/intel/cannonlake: Add PchPmPwrCycDur to chip options	Sridhar Siricilla
2020-06-25	drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1	Jonathan Zhang
2020-06-25	soc/intel/xeon_sp: use edk2-stable202005 headers	Jonathan Zhang
2020-06-25	soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs	Jonathan Zhang
2020-06-25	soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE define	Edward O'Callaghan
2020-06-24	soc/intel/tigerlake: Fix unresolved symbol CDW1 error	John Zhao
2020-06-24	soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register	Elyes HAOUAS
2020-06-24	src: Report byte-sized access for GPE0	Angel Pons
2020-06-24	ACPI: Replace smm_setup_structures()	Kyösti Mälkki
2020-06-24	ACPI: Replace uses of CBMEM_ID_ACPI_GNVS	Kyösti Mälkki
2020-06-22	soc/intel/tigerlake: Add CmdMirror option in chip.h	David Wu
2020-06-22	soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count()	Jonathan Zhang
2020-06-22	mb/google/volteer: Override power limits with SKU-specific limits	Tim Wawrzynczak
2020-06-22	soc/intel/xeon_sp/cpx: consider stack personality	Jonathan Zhang
2020-06-22	soc/intel/xeon_sp/cpx: update ACPI xSDT	Jonathan Zhang
2020-06-22	soc/intel/jasperlake: add processor power limits control support	Sumeet R Pawnikar
2020-06-22	soc/intel/xeon_sp/cpx: Finalize PCU configuration	Jonathan Zhang
2020-06-22	soc/intel/tigerlake: Update platform.asl to ASL2.0 syntax	V Sowmya
2020-06-22	device/smbus_host: Declare common early SMBus prototypes	Kyösti Mälkki
2020-06-22	cpu/x86/smm: Define APM_CNT_NOOP_SMI	Kyösti Mälkki
2020-06-22	soc/intel/broadwell/systemagent.c: Fix typo	Angel Pons
2020-06-20	ACPI: Drop some HAVE_ACPI_RESUME preprocessor use	Kyösti Mälkki
2020-06-19	soc/intel/tigerlake: Update TCSS for SW CM support	John Zhao
2020-06-19	soc/intel/common/acpi: rename dptf.asl to dptf_common.asl file	Sumeet R Pawnikar
2020-06-19	tigerlake: add unique acpi device ids for dptf	Sumeet R Pawnikar
2020-06-19	Kconfig: Escape variable to accommodate new Kconfig versions	Patrick Georgi
2020-06-18	soc/intel,chromeos: Fix EC RO/RW status in GNVS	Kyösti Mälkki
2020-06-18	soc/intel/tigerlake: Enable FSP-S compression	Karthikeyan Ramasubramanian
2020-06-18	soc/intel/jasperlake: Enable FSP-S compression	Karthikeyan Ramasubramanian
2020-06-18	soc/intel/cannonlake: Enable FSP-S compression	Karthikeyan Ramasubramanian
2020-06-18	soc/intel: remove unused dptf.asl file and other defines	Sumeet R Pawnikar
2020-06-18	soc/intel/common: make dptf acpi device ids configurable	Sumeet R Pawnikar
2020-06-18	soc/intel/common: Introduce ASL2.0 syntax	Alexey Buyanov
2020-06-17	soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD	Wonkyu Kim
2020-06-17	soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimit	Patrick Rudolph
2020-06-17	soc/intel/cannonlake: Use table instead of switch-case	Patrick Rudolph
2020-06-16	cpu/x86: Define MTRR_CAP_PRMRR	Kyösti Mälkki
2020-06-16	sb,soc/intel: Replace smm_southbridge_enable_smi()	Kyösti Mälkki
2020-06-16	soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)	Kyösti Mälkki
2020-06-16	sb/intel: Remove spurious HAVE_SMI_HANDLER test	Kyösti Mälkki
2020-06-16	arch/x86: Create helper for APM_CNT SMI triggers	Kyösti Mälkki
2020-06-15	arch/x86: Remove NO_FIXED_XIP_ROM_SIZE	Kyösti Mälkki
2020-06-14	soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS	Jonathan Zhang
2020-06-14	soc/intel/tigerlake: enable CPU_INTEL_COMMON	Alex Levin
2020-06-14	soc/intel/cannonlake/acpi: Capitalize hex number to unify with Skylake	Paul Menzel
2020-06-14	soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add cpu entries in ssdt	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: fix MADT ACPI table	Jonathan Zhang