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path: root/src/soc/intel
AgeCommit message (Expand)Author
2021-05-13src: Match array format in function declarations and definitionsPatrick Georgi
2021-05-11docs: correct and rewrite documentation regarding n/c / unused padsMichael Niewöhner
2021-05-10src: Drop "This file is part of the coreboot project" linesAngel Pons
2021-05-10soc/intel/cannonlake: Merge soc_memory_init_params() into its callerFelix Singer
2021-05-10soc/intel/skylake: Set proper defaults in chipset devicetreeFelix Singer
2021-05-10soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetrainingMaulik V Vaghela
2021-05-07soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen
2021-05-07soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen
2021-05-06src: Retype option API to use unsigned integersAngel Pons
2021-05-06Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"Arthur Heymans
2021-05-06soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak
2021-05-06soc/intel/tigkerlake: Add IOM PCR PIDTim Wawrzynczak
2021-05-06soc/intel/tigerlake: Add known CPU Port IDs for GPIO communitiesTim Wawrzynczak
2021-05-06soc/intel/common: Add CPU Port ID field to GPIO communitiesTim Wawrzynczak
2021-05-06soc/intel/tigerlake: Add known GPIO virtual wire informationTim Wawrzynczak
2021-05-06soc/intel/common: Add virtual wire mapping entries to GPIO communitiesTim Wawrzynczak
2021-05-06soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo
2021-05-05soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIOMaulik V Vaghela
2021-05-05soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 regMaulik V Vaghela
2021-05-05drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans
2021-05-05soc/intel/xeon_sp: Remove bogus SMRAM lockingArthur Heymans
2021-05-04soc/intel/alderlake: remove duplicate PL2 overrideSumeet R Pawnikar
2021-05-03soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
2021-05-03soc/intel/alderlake: Enable HWP CPPC support in CBravindr1
2021-05-03soc/intel/alderlake: Fill FSPM UPDs for VT-d configurationMeera Ravindranath
2021-05-02soc/intel/cannonlake/include: Drop unused codeFelix Singer
2021-05-02soc/intel/skylake: Remove useless help textsFelix Singer
2021-05-02soc/intel/cannonlake: Remove useless help textsFelix Singer
2021-05-01soc/intel/skylake: Add Kconfig option for LGA1151v2Timofey Komarov
2021-05-01soc/intel/skylake: Add microcodes for Coffee Lake CPUsTimofey Komarov
2021-04-28soc/intel/common/block/hda: Use azalia device codePatrick Rudolph
2021-04-28soc/intel: Add Z370, H310C and B365 device IDsAngel Pons
2021-04-28soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons
2021-04-28soc/intel/skylake: Shorten report_platform PCH-H namesAngel Pons
2021-04-28soc/intel: Rename 200-series PCH device IDsAngel Pons
2021-04-28soc/intel/skylake: Drop Lewisburg PCHs from report_platformAngel Pons
2021-04-26haswell/broadwell: Replace remaining MCHBAR accessorsAngel Pons
2021-04-26soc/intel/elkhartlake: Remove elog.cTan, Lean Sheng
2021-04-26soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng
2021-04-26soc/intel/alderlake: Use device ID from pci_devs header fileJohn Zhao
2021-04-26soc/intel/alderlake: Fix devices list in the DMAR DRHD structureJohn Zhao
2021-04-26soc/intel/tigerlake: Use device ID from pci_devs header fileJohn Zhao
2021-04-23soc/intel/xeon_sp/cpx: Add UPI locksMarc Jones
2021-04-23soc/intel/xeon_sp/cpx: Add IMC locksMarc Jones
2021-04-23soc/intel/jasperlake: Remove TCSS setting from the DMAR tableJohn Zhao
2021-04-23soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoCSumeet R Pawnikar
2021-04-23soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structureAngel Pons
2021-04-22soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POSTMichael Niewöhner
2021-04-22soc/intel/skylake: set MSR LT_LOCK_MEMORY only when using native MP initMichael Niewöhner