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2019-01-28soc/intel/denverton_ns: Add ACPI T-States and P-StatesJulien Viard de Galbert
Also make soc_get_tss_table public and weak instead of static in intelblock so it can be overridden in denverton. Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-28soc/intel/{apl,skl}: Drop redundant `select RTC`Nico Huber
RTC is now implicitly selected through SOC_INTEL_COMMON_BLOCK_RTC and SOC_INTEL_COMMON_PCH_BASE. Change-Id: I1885c419cfe318b75f3bda6220d4a6f6a8e26575 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-28soc/intel/common/rtc: Enable RTC in common code RTCLijian Zhao
Intel RTC common code driver need to turn on RTC itself.After the change, cannonlake and icelake platform will have RTC enabled. BUG=b:123372643 TEST=build and boot up on sarien platform, check .config to see CONFIG_RTC is set. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I0c8c5cf9e6f7f338b1f2f784c04254649d257536 Reviewed-on: https://review.coreboot.org/c/31112 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28src/soc/intel/cnl/chip.h: Fix preprocessor conditionAngel Pons
Commit dc666f5 (soc/intel/cannonlake: Change in SaGv options) added a conditional preprocessor directive, but its condition was incorrect because SOC_INTEL_CANNONLAKE is selected for CNL, CFL and WHL. Thus, an explicit check for !SOC_INTEL_COFFEELAKE is required. While we are at it, clean up the comment above a bit. BUG=b:123184474 Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31095 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-27src: Fix the warning "type 'hex' are always defined"Elyes HAOUAS
This is spotted using "./util/lint/kconfig_lint" While at it, do the check in C and not the preprocessor. Change-Id: Icfda267936a23d9d14832116d67571f42f685906 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-25soc/intel/denverton_ns: Enable ACPI using intelblockJulien Viard de Galbert
- Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25soc/intel/cannonlake: Export function to set After G3 stateDuncan Laurie
Export the SOC level function to set the After G3 state so it can be changed by the mainboard. The setting will be restored by a normal boot but in some circumstances coreboot wants to ensure that it will be powered up again after a reset. BUG=b:121380403 TEST=update cr50 firmware on sarien and reboot and ensure the host does not power off after the cr50 initiated reset. Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31056 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25soc/intel/cannonlake: Disable CpuRatio and SaGv in recoveryDuncan Laurie
Disabling CpuRatio UPD for FSP will ensure it does not force a hard reset to set the CPU Flex Ratio at boot. This is important in a recovery mode boot where the SOC will lose power and need to set the flex ratio again. Disabling SaGv makes recovery mode training faster and mirrors the setting that was done on Skylake. BUG=b:123305400 TEST=reliably enter recovery mode on sarien Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-25soc/intel/apollolake: Override GLK usb clock gating registerJohn Zhao
It was observed system suspend/resume failure while running RunInDozingStress. Apply correct GLK usb clock gating register value to mitigate the failure. BRANCH=octopus BUG=b:120526309 TEST=Verified GLK clock gating register value after booting to kernel. Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib"Patrick Georgi
This reverts commit ab1227226ebd78b40783cb200e60711b900352f0. There were significant changes around soc_reset_tco_status() that this code needs to be adapted to. Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24soc/intel/denverton_ns: Configure MCAJulien Viard de Galbert
Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25433 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Use cpulib in cpu.cJulien Viard de Galbert
Also remove duplicate code Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25432 Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Enable Fast StringsJulien Viard de Galbert
Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25431 Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Rewrite pmutil using pmclibJulien Viard de Galbert
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25427 Reviewed-by: David Guckian Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/common/block/acpi: fix P-States extra entryJulien Viard de Galbert
The ratio_max step is appearing twice when (ratio_max - ratio_min) is evenly divisible by the ratio step. This is because in this case there are no rounding down of ratio_max in the for loop. Thanks Jay Talbott for the step calculation algorithm. Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-24soc/intel/gpio: Enable configuring GPIO debounce durationKarthikeyan Ramasubramanian
Add new helper macros to enable configuring debounce duration for a GPIO input. Also ensure that the debounce configuration is not masked out. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce duration is configured as expected. Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad registerKarthikeyan Ramasubramanian
Currently all the helpers support configuring GPIO_DW0/1 registers. In some architectures there is an additional configuration GPIO_DW2 register that can be used to configure debounce duration etc. Add a helper macro to enable configuring GPIO_DW2 pad register. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the current configuration is not disturbed by turning on the GPIO_DEBUG option and verifying the debug output before and after the change. Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar
Replace device name from B0D4 with TCPU for DPTF sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I962d74fc1baa07581d065734aaabb4dcd5e3d247 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-23soc/intel/baytrail/romstage: Remove unneeded white spaceElyes HAOUAS
Change-Id: I6725d1130a40d3c458a3cd5a116d6e91354ec41b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23soc/{amd,intel}: Remove needless '&' on function pointersElyes HAOUAS
Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2019-01-23Drop leftover debug function declarationsKyösti Mälkki
Change-Id: Ib93b816e7ab3146f6f70ad4089327cd6b7bc7c24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-21drivers/spi: Add controller protection typeRizwan Qureshi
Some SPI controllers support both READ and WRITE protection add a variable to the protect API for the callers to specify the kind of protection they want (Read/Write/Both). Also, update the callers and protect API implementation. BUG=None BRANCH=None TEST=test that the mrc cache is protected as expected on soraka. Also tried if the read protection is applied correctly. Change-Id: I093884c4768b08a378f21242ac82e430ac013d15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-20src/soc/intel/braswell: Use DEVICE_NOOPElyes HAOUAS
Use already defined DEVICE_NOOP instead. Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29857 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLEVanessa Eusebio
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-on: https://review.coreboot.org/c/26928 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17soc/intel/cannonlake: drop extra newlinePatrick Georgi
Change-Id: I614ea7f0f74326e306649779266001cf25ce5e07 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-01-17soc/intel/cannonlake: Change in SaGv optionsRonak Kanabar
CNL,WHL and CFL all are not using midfixed option in SaGv so keeping it for CNL only and removing it for others. Change-Id: I754515c2f8e249479c603872c61ac9a006e962ff Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/30917 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17soc/intel/icelake: Fix AG3E programming in PMCLijian Zhao
According to EDS #571034 4.3.2, GEN_PMCON_A stays in pmc mmio mapped register but not pci configuration spaces, hence change the programming method in icelake pmc driver. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7 Reviewed-on: https://review.coreboot.org/c/30947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-17soc/intel/fsp_broadwell_de: Enable FIT supportPatrick Rudolph
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Tested on wedge100s. Microcode is placed in FIT. Change-Id: Ie0003f597aa5f272847b4f8895a1e3571caa3464 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30956 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17soc/intel/fsp_broadwell_de: Fix TSEG size computationPatrick Rudolph
The address bits 19:0 of TSEG_LIMIT read as zero, but are ignored on comparison. The result is that the limit is effectively FFFFFh. Add one MiB to the register value to make TSEG 8MiB instead of 7MiB. Fixes a crash related to SMRR not matching the TSEG region. Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-16soc/intel/cannonlake: Fix afterg3 programmingLijian Zhao
According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC memory mapped register but not pci config spaces. Change the programming to affect that difference. BUG=b:122425492 TEST=Change System Power State after failure to "s5 off", and boot up onto sarien platform, check the register with iotools mmio_read32 0xfe001020 and bit 0 is set. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e Reviewed-on: https://review.coreboot.org/c/30945 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16soc/intel/skylake: Access conf pointer only if its not nullPratik Prajapati
conf pointer could be null, access it only if its not null. Foundby=klocwork BUG=N/A TEST=N/A Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015 Reviewed-on: https://review.coreboot.org/c/30862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-16soc/intel/cannonlake: Access conf pointer only if its not nullPratik Prajapati
conf pointer could be null, access it only if its not null. Foundby=klocwork BUG=N/A TEST=N/A Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I1b3d6f53d2bfd9845ad7def91c4e6ca92651d216 Reviewed-on: https://review.coreboot.org/c/30860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-16soc/intel/cannonlake: Add processor power limits control supportSumeet Pawnikar
Add processor power limits control support to configure values. BRANCH=None BUG=b:122343940 TEST=Built and tested on Arcada system Change-Id: I5990dc05b51481a0074855914cef20cf07378cde Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-15soc/intel/apl: Hook microcode updates upNico Huber
Only tested on APL. Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-15vendorcode/intel/fsp1_0/broadwell_de: Use FSP from 3rdparty/fspPatrick Rudolph
Default to FSP binary and headers shiped in 3rdparty/fsp. * Drop headers and code from vendorcode/intel/fsp1_0/broadwell_de * Select HAVE_FSP_BIN to build test the platform * Fetch FSP repo as submodule * Make FSP_HEADER_PATH known from FSP2.0 useable on FSP1.0 * Introduce FSP_SRC_PATH for FSP source file * Add sane defaults for FSP_FILE Tested on wedge100s. Change-Id: I46f201218d19cf34c43a04f57458f474d8c3340d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-14soc/intel/cannonlake: Provide interface to update TCC offsetJohn Su
This change provides an interface for canonlake to set TCC. With this change, we can add code to update Tcc in devicetree. BUG=b:122636962 TEST=Match the result from TAT UI Change-Id: Ib54a118e4e409919e3e60112e4621a109404b16d Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-14console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber
Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Beside Qemu targets, the only platforms that didn't select it seem to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The latter two were about to be patched anyway. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30891 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14soc/intel/apollolake: Add option to disable xHCI Link Compliance ModeJohn Zhao
Provide options to disable xHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. BRANCH=octopus BUG=b:115699781 TEST=Verified booting to kernel. Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30816 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()Patrick Rudolph
Move early_mainboard_romstage_entry before console_init. Allows to setup a SuperIO, if any, for serial console. Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14intel/fsp1_0: Add option to select FSP debug levelPatrick Rudolph
Useful for debugging FSP. Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-14soc/intel/fsp_broadwell_de: Fix uartPatrick Rudolph
* Disable FSP serial output if not CONSOLE_SERIAL Tested on wedge100s. Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-13{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()Elyes HAOUAS
Use hexdump() instead of dump_mem(). Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-12soc/intel/cannonlake: Hook up MicrocodeLijian Zhao
Hook Coffeelake U43e and Coffeelake H/S/E3 microcode into SOC and remove the MICROCODE_BLOB_NOT_HOOKED_UP. BUG=N/A TEST=Boot up with coffeelake rvp board and check microcode revision in coreboot log. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I6593081374dd4898a82db5b43c3b5bf154b3ef60 Reviewed-on: https://review.coreboot.org/c/30864 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10soc/intel/fsp_broadwell_de: Drop MICROCODE_BLOB_NOT_HOOKED_UPNico Huber
It's been hooked up in the meantime. Change-Id: I64176b09e375034189000ea4308c58771f0019a1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30812 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TOPatrick Georgi
TCO2_STS_SECOND_TO was renamed to TCO_STS_SECOND_TO but one use slipped through. Change-Id: I9e3b1cc5cb2f319db35416edf6cea612d755d40a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30805 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10soc/intel/fsp_broadwell_de/vtd: Silence warningPatrick Rudolph
Silence PCI resource warning due to missing set_resources. Change-Id: I8253e9ca137bda1cdd1c06273679693c4b7803ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-10soc/intel/denverton_ns: Fix missing tsc_freq_mhz()Kyösti Mälkki
It was relying on bad weak implementation for postcar and verstage. Change-Id: I5a520e0166198c0565349c164f143f4a43649861 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Guckian Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
2019-01-10Untangle CBFS microcode updatesNico Huber
The option to specify a binary file name was added later for platforms that do not provide microcode updates in our blobs repository. Alas, it wasn't visible what platforms these are. And if you specified a file for a platform that already had one, they were all included together. Make it visible which platforms don't provide binaries with the new con- figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to include binaries by default or explicitly show that no files are inclu- ded (default to CPU_MICROCODE_CBFS_NONE). Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS. And clean up the visibility of options: Don't show CBFS related options on platforms that don't support it and don't show external file options if the platform uses special rules for multiple files (CPU_MICROCODE_ MULTIPLE_FILES). Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29934 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-13 10:29:23 +0000