coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-12	soc/intel/skylake: Add ability to set root port ASPM	Wim Vervoorn
2020-05-12	soc/intel/tigerlake: Correct IRQ interrupt	Wonkyu Kim
2020-05-12	device/pci_device: Extract pci_domain_set_resources from SOC	Raul E Rangel
2020-05-12	soc/intel/jasperlake: Remove deprecated UPDs	Ronak Kanabar
2020-05-12	soc/intel/jasperlake: Add SATA related UPDs configuration	Ronak Kanabar
2020-05-12	soc/intel/tigerlake: Control SATA and DMI power optimization	Shaunak Saha
2020-05-12	soc/intel/skl: Drop weak mainboard_memory_init_params	Angel Pons
2020-05-11	soc/intel/quark: Revamp file headers	Patrick Georgi
2020-05-11	treewide: Replace BSD-3-Clause and ISC headers with SPDX headers	Patrick Georgi
2020-05-11	treewide: split off license text, remove extra copyright notices	Patrick Georgi
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-11	soc/intel/skylake: Allow setting of PcieRpMaxPayload	Wim Vervoorn
2020-05-11	soc/intel/tigerlake: Update C-State info	Wonkyu Kim
2020-05-11	soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX	Michael Niewöhner
2020-05-11	soc/intel/jasperlake: Add ACPI device name for Storage controllers	Karthikeyan Ramasubramanian
2020-05-11	soc/intel/jasperlake: Enable end of post support in FSP	Aamir Bohra
2020-05-10	src: Replace remaining GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-05-09	vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()	Julius Werner
2020-05-08	{security,soc}/*/Kconfig: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-05-08	soc/intel: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-05-08	soc/intel/skl: Drop `acpi_mainboard_gnvs`	Angel Pons
2020-05-07	soc/intel/tigerlake: Add PMC to platform ACPI name entry	John Zhao
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-05-06	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha
2020-05-06	soc/intel/tigerlake: Print HPR_CAUSE0 register	derek.huang
2020-05-05	soc/intel/jasperlake: Correct the EMMC PCR Port ID	Ronak Kanabar
2020-05-05	soc/intel/jasperlake: Allow SD card power enable polarity configuration	Ronak Kanabar
2020-05-05	soc/intel/tigerlake: Add PMC mux control	John Zhao
2020-05-04	soc/intel/tigerlake: Update interrupt setting	Wonkyu Kim
2020-05-04	src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M	Srinidhi N Kaushik
2020-05-04	soc/intel/skl: always enable SataPwrOptEnable	Michael Niewöhner
2020-05-04	soc/intel/cannonlake: Add DisableHeciRetry to config	Christian Walter
2020-05-04	soc/intel/common/block/cse: Add boot partition related APIs	Sridhar Siricilla
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
2020-05-01	soc/intel/xeon_sp/cpx: Implement hide/unhide P2SB traditional dance	Andrey Petrov
2020-05-01	soc/intel/xeon_sp/cpx: Enable common P2SB	Andrey Petrov
2020-05-01	soc/intel/xeon_sp: Add C620 p2sb.h	Andrey Petrov
2020-05-01	xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs	Maxim Polyakov
2020-05-01	soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-05-01	soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-05-01	soc/intel/braswell: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-05-01	soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-05-01	soc/intel/common: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-05-01	soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-05-01	soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...	Subrata Banik
2020-05-01	soc/intel/jasperlake: fix args of dimm_info_fill() for dram_part_num	Marco Chen
2020-05-01	soc/intel/cannonlake/bootblock: Fix FSP CAR	Patrick Rudolph
2020-05-01	soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree	Meera Ravindranath