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Change-Id: I6dd004b417c27ff0b9f7e55557a9670f927d425c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ide01a922d7d8e500f9a0b507544010706661d7de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40690
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop unused includes and add missing <intelblocks/systemagent.h>.
Change-Id: I06c8b2bf65283c3c1fcd25fdaae298b82fc0e09c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Change-Id: I57e064d26b215743a1cb06bb6605fc4fe1160876
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41491
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'.
Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI bar was not programmed previously for which is needed to enable SMI's and
to check SMI status registers. The architecture of Lewisburg PCH is very
similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.
TEST=build for Tiogapass and check ACPI base. Log message will now show
pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing
to io port 0x500.
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries.
Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40842
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement triggering recovery mode for CSE Lite SKU runtime errors. Also,
define recovery subcodes for various possible Lite SKU runtime errors.
BUG=b:153520354
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib7744fc4fd0e41804d9b45079bf706b300220c62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I8877a70661cacc57ea893da172d9a4b6d19ba06a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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This change updates pch_hda.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
BUG=none
BRANCH=none
TEST="BUILD for Volteer"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ia2bab6dcbac9eae76ac4258c44bb19425c8b5c80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
BUG=none
BRANCH=none
TEST="BUILD for volteer"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.
BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ChromeOS EC is adding new entries to its USBC.CONx devices (see later
patch), and it needs to get access to the PMC.MUX device so that its
ACPI path can be retrieved. This provides a weak function to return NULL
for all Intel SoCs except for Tiger Lake, which locates the device if it
is found in the devicetree.
Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In an attempt to help reduce the amount of static ASL files that are
littered throughout the codebase, pmc.asl was converted to runtime SSDT
generation instead. If future SoCs reuse the same PMC, then this
function can be moved to soc/intel/common/block/pmc for example.
TEST=Verified the following was in the decompiled SSDT:
Scope (\_SB.PCI0)
{
Device (PMC)
{
Name (_HID, "INTC1026") // _HID: Hardware ID
Name (_DDN, "Intel(R) Tiger Lake IPC Controller")
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0xFE000000, // Address Base
0x00010000, // Address Length
)
})
}
}
Also the following found in linux's /var/log/messages:
"acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC
ACPI device was found and its _CRS was locatable.
Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This patch will disable PAVP UPD, which is by default enabled in FSP.
BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD values from FSP log
Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41763
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Current implementation returns the incorrect GPIO community PID.
The GPIO community index 3 should return PID for COMM_4 and index
4 should return PID for COMM_5.
TEST=Verify GPIO PM bits are correctly set through MS0x ACPI method.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I3da4945e93605a297baff076295433164fdf613d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41721
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable/Disable THCx though devicetree
BUG=None
BRANCH=None
TEST=Boot and check FSP log for THC setting
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: If7683969161be67f68f441c28c80503de39079b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Current implementation returns the incorrect GPIO community PID.
The GPIO community index 3 should return PID for COMM_4 and index
4 should return PID for COMM_5.
TEST=Verify PCR port id is correct for each community.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5dc48e5b31f43853b3a613c17f13f7df71f1fbfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41725
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6c69dcad82ee217ed4760dea1792dd1a6612cd8b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The declaration is autogenerated inside static.c file
from the pathname. The declaration here also lacked _skx_
part from the name.
Change-Id: I3adce9147e9376f6d73e410fdd4c0ee800178b58
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The declaration is autogenerated inside static.c file
from the pathname.
Change-Id: I6eda101a69522d6d526da7c174aa3085ca0fb221
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use CAPID0_A to provide information closer to reality.
* Correctly advertise ECC support, max DIMM count and max capacity
* CAPID0_A hasn't changed since SNB, but most EDS mark the bits as
reserved even though they are still used by FSP.
* Assume the same bits for Tiger Lake as for Ice Lake
* Assume the same bits for Skylake as for Coffee Lake
* Add CAPID0_A to Icelake headers
The lastest complete documentation can be found in Document: 341078-002.
Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Allow lockdown configuration from using CHIPSET_LOCKDOWN_COREBOOT
config.
TEST=Build and boot waddledoo board
Change-Id: I3abaa737580ef45b98cabfa23edd84162037dd70
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`fsp/util.h` draws incompatible UDK headers in. Hence, we have to
declare it locally again.
Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0572dbbfb61e5e0129fe6a3a1b5894145d74fd0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40728
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also fix wrong 32-bit writes.
Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The allocator should take care of this.
Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I359b529df44db7d63c5a7922cb1ebd8e130d0c43
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40725
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It never was in GNVS, it never belonged among the ACPI tables. Having
it in CBMEM, makes it easy to look the location up on resume, and saves
us additional boilerplate.
TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and
intel_backlight + acpi_video synchronize, both before and
after suspend.
Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select UDK_2017_BINDING instead of UDK_2015_BIDING. Otherwise
there is build error when turning on FSP debugging.
Remove duplicate configs from SKX-SP and CPX-SP directories, to
keep the configs at SoC family level.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I6b25bf25dcb57937e2d9fec54eeb7951b0ee4b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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In Tiger Lake we have support for enabling MIPI clocks at runtime in
ACPI. Hence remove setting pch_islclk from devcietree and chip.h.
Also update functions which reference pch_isclk.
BUG=b:148884060
Branch=None
Test=build and boot volteer and verify camera functionality
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Delete below configuration
- Heci3Enabled: deprecated,
see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442
- PchIshEnable: don't need as it's handled by devicetree dev on/off,
see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87
BUG:b:151166877
BRANCH=none
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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It's already disabled by FSP default but disable VMD by devicetree
to remove dependency with FSP default setting.
BUG=None
Branch=None
Test=Build TGLRVP and boot up and check FSP log for checking VMD is
disabled.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update processor power limit configuration parameters based on
common code base support for Intel Apollo Lake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on octopus system
Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds FSP UPD D3HotEnable and D3ColdEnable for configuration.
D3Hot low power mode support is for TCSS xhci, xdci, TBT PCIe root
ports and DMA controllers. D3Cold is lower mode for TBT PCIe root
ports and DMA controllers with D3Hot->D3Cold transition.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I6782cde6a1bfe13f46e75db8c85537c6d62f5d41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Change-Id: I2d0c90afe8acf8405da2cb6444e47dc98ad8cc9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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After removal of CAR_MIGRATION there are no more reasons
to carry around ENV_STAGE_HAS_BSS_SECTION=n case.
Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit
zero-initializers.
Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update processor power limit configuration parameters based on
common code base support for Intel Cannonlake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on drallion system
Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation
region to be SystemIO and ACPI_BASE_ADDRESS.
BUG=b:156530805
TEST=Built and booted to kernel.
Signed-off-by: John zhao <john.zhao@intel.com>
Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The
BIOS needs to program VrPowerDeliverDesign configuration per platform
according to the platform capabilities to avoid incorrect
electrial/power parameters. This is only added for Cannon Lake.
Refer to document 599797 for more details.
Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some existing devicetrees were manually adapted to anticipate
root-port switching. Now, their PCI-device on/off settings should
just reflect the `PcieRpEnable` state and configuration happens
on the PCI function that was assigned at reset.
Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Current Interrupt setting use 2nd parameters as device function number.
Correct as interrupt pin number according to _PRT package format.
{Address, pin, Source, Source index}
Reference:
- ACPI spec 6.2.13 _PRT
BUG=None
BRANCH=None
TEST=Build and boot JSLRVP Verify Interrupt mappings are same as PCI
INTR(0x3C) register and no interrupt storm is seen
Change-Id: I21462c6befea310a49eecf9ad1b5c8770eccd5bd
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41404
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifbab50ef42f0fe49dd3949db662b245c63522f2d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41599
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch provides an option for accommodating 64 bit width resource
request with CONFIG_PCI_SEGMENT_GROUPS = 16 refer as PCIEX BAR length 4096MB
(Bus 0-4095).
Change-Id: I9a8448af7e9f26c8e0176e58e4fe253a6e77b69a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40336
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix
*** Pre-CBMEM romstage console overflowed, log truncated! ***
issue.
TEST=Verified on TGL platform.
Change-Id: Iae66b6a1260a9290b35d804487b7a07242c5ebc2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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The Intel Tigerlake SoundWire controller has 4 master links which
are configured differently depending on the external crystal oscillator
which is connected to the PCH.
This function will read the PCH PMC EPOC register to determine the
frequency and then fill out the master link entries with the correct
table values.
The frequency is also provided directly in a custom "ip-clock" property
which will be added to the link descriptor and passed to the OS driver
so it can know the clock rate of the master.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I98b7df21210c29cd8defeff648f2c2207d629295
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The PMC EPOC register indicates which external crystal oscillator is
connected to the PCH. This frequency is important for determining the
IP clock of internal PCH devices.
Add definitions that allow this register to be read and extract the
crystal frequency, and a helper function to extract and return this
as the defined enum.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I959fe507f3dbf93b6176b333a9e725ed09f56328
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40887
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The audio devices are currently set to enable static devices at their
own level, but in order to supported nested SoundWire devices these
drivers must instead use scan_static_bus. Without this change the
device tree code will not look at children of these devices.
After this change the audio device can have nested devices:
device pci 1f.3 on
chip drivers/intel/soundwire
device generic 0 on end
end
end
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ibb716fbd9ffdc45f2c4bbe5e81f420ec2b13483c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable DPTF functionality for volteer platform
BRANCH=None
BUG=b:149722146
TEST=Built and tested on volteer system
Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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