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path: root/src/soc/intel
AgeCommit message (Expand)Author
2015-04-30intel/broadwell: Build monotonic timer driver for SMMPatrick Georgi
2015-04-30chromeos: Add missing headersPatrick Georgi
2015-04-30kbuild: Don't require intel/common changes for every socStefan Reinauer
2015-04-29kbuild: automatically include SOCsStefan Reinauer
2015-04-28fsp platforms: consolidate FspNotify callsMartin Roth
2015-04-27intel/fsp_baytrail: Fix default SMM_TSEG_SIZE valueDavid Imhoff
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
2015-04-22intel/broadwell: guard CHROMEOS support betterPatrick Georgi
2015-04-22coreboot: common stage cacheAaron Durbin
2015-04-21broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.Todd Broch
2015-04-21broadwell: indent xhci codePatrick Georgi
2015-04-21broadwell: Skip pre-graphics delay in resume pathDuncan Laurie
2015-04-21broadwell: Implement Recovery ButtonRyan Lin
2015-04-18broadwell: Set C9/C10 vccminDuncan Laurie
2015-04-18broadwell: Disable XHCI compliance mode entryDuncan Laurie
2015-04-18soc/intel/common: Add common reset codeLee Leahy
2015-04-18soc/intel/common: Add function to protect MRC cacheDuncan Laurie
2015-04-18broadwell: add ROM stage pre console init call backWenkai Du
2015-04-15broadwell: Fixes for _SWS supportDuncan Laurie
2015-04-15broadwell: Remove unused bootblock codeDuncan Laurie
2015-04-15broadwell: Clean up ME device and add new ME10 flowDuncan Laurie
2015-04-15soc/baytrail: Use microcode from the blobs repositoryMarc Jones
2015-04-15soc/broadwell: Use microcode from the blobs repositoryMarc Jones
2015-04-14broadwell: Remove TPM device from lpc.aslDuncan Laurie
2015-04-13broadwell: Work around VBIOS framebuffer issueDuncan Laurie
2015-04-13broadwell: Fix incorrect SATA port map maskWenkai Du
2015-04-13broadwell: Enable double self refresh by defaultDuncan Laurie
2015-04-10baytrail: correct NC pin to GPO pin according to BYT platform design guideKane Chen
2015-04-10broadwell: Correct XHCI offset for USB 3.0 portsJulius Werner
2015-04-10broadwell: Set PCIe replay timeout to 0xDDuncan Laurie
2015-04-10baytrail: add code for supporting 2x ddr refresh rateKane Chen
2015-04-10broadwell: Add configuration for tuning VR for C-state operationsDuncan Laurie
2015-04-10broadwell: Preserve VbNv around cmos_initDuncan Laurie
2015-04-10broadwell: Add function to apply PRR to a range of SPI flashDuncan Laurie
2015-04-10broadwell: Turn off panel backlight in S5 SMI handlerDuncan Laurie
2015-04-10broadwell: Skip steps when disabling PCIe portDuncan Laurie
2015-04-10broadwell: Remove XHCI workarounds on WPTDuncan Laurie
2015-04-10broadwell: Only do pre-graphics delay when running option romDuncan Laurie
2015-04-10broadwell: Fix PCIe ports programming sequences to enable HSIOPCWenkai Du
2015-04-10broadwell: Update SATA Gen3 TX adjustment registersDuncan Laurie
2015-04-10broadwell: Add a few bits to finalize stepDuncan Laurie
2015-04-10baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee
2015-04-10Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh
2015-04-10Broadwell: Set boot_mode of pei_data before running reference codeKenji Chen
2015-04-10broadwell: Increase I2C SDA hold timing to 300nsChiranjeevi Rapolu
2015-04-10broadwell: add RCBA posting read after writingWenkai Du
2015-04-10Broadwell: Synchronization with FRC for Root Port Power ManagementKenji Chen
2015-04-10broadwell: Skip DDI-A enable in S3 resumeDuncan Laurie
2015-04-10broadwell: Add support for ACPI \_GPE._SWSDuncan Laurie
2015-04-10baytrail: Switch from ACPI mode to PCI mode for legacy supportMarc Jones
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