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2017-10-03soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao
Add ACPI dsdt table for northbridge, report proper resources in dsdt entries. TEST=Boot up into OS fine. Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Fill the SMI usageLijian Zhao
Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Add lpc pci driverLijian Zhao
1.Add common ITSS support as part of LPC driver init code. 2.Add LPC pci driver for CNL Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/skylake: Enable common LPC IPRavi Sarawadi
Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/common/block: Update LPC libRavi Sarawadi
Add support for following functionality: 1. Set up PCH LPC interrupt routing. 2. Set up generic IO decoder range settings. 3. Enable CLKRUN_EN for power gating LPC. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02soc/intel/common/block: Move power button SMI functions to common PMC blockShaunak Saha
This patch moves the functions update_pm1_enable and read_pm1_enable to common block PMC. We rename the functions to pmc_update_pm1_enable and pmc_read_pm1_enable to keep semantics consistent. Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-02soc/intel/skylake: Use common/block/gpioHannah Williams
Other than switch to use common gpio implementation for skylake based platform, also apply the needed changes for purism board. Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30soc/intel/braswell/acpi: Clean OpRegion upPatrick Rudolph
Reorder code and put platform specific bits into update_igd_opregion. Get rid of get_fsp_vbt and init_igd_opregion. Write GMA opregion in case a VBT was provided, even when no FSP_GOP is to be run. Use SOC_INTEL_COMMON_GFX_OPREGION to reduce code duplication. Change-Id: Ibabeb05a9d3d776b73f6885dcca846d5001116e7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27soc/intel/skylake: Remove CCA object for IMGU and CIO2 devicesV Sowmya
IMGU and CIO2 devices do support the hardware managed cache coherency and hence removing the CCA object which was reporting that cache coherency is not supported. BUG=none BRANCH=none TEST=Build and boot soraka. Dump ACPI tables and verify that CCA object is not present. Change-Id: I14b0a92eafe193e9004d2dad0957a3fe8d05d313 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27soc/intel/common: Add Cannonlake PCI idLijian Zhao
Add extra pci ids of CNLU and CNLY into common code. Change-Id: Ibbf3d500a780cc6a758fda1ddbec2b9953fb5a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27soc/intel/apollolake: Add SGX supportPratik Prajapati
- Call into commmon SGX code to configure core PRMRR and follow other SGX init seqeuence. - Enable SOC_INTEL_COMMON_BLOCK_SGX for both GLK - Enable SOC_INTEL_COMMON_BLOCK_CPU_MPINIT for GLK, as MP init needs to be completed before calling into fsp-s for SGX. Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-09-27soc/intel/apollolake: Add PrmrrSize and SGX enable configPratik Prajapati
Add PrmrrSize and sgx_enable config option. PrmrrSize gets configured in romstage so that FSP can allocate memory for SGX. Also, adjust cbmem_top() calculation. Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-09-27soc/intel/cannonlake: Add FSP GOP supportAbhay kumar
1. Add FSP GOP config. 2. Pass VBT to FSP. Change-Id: Icf836d683ae00cd034c853bc9ce965d4de5f7413 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/21628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-25soc/intel: lpc: Use IS_POWER_OF_2 instead of open-coding itJonathan Neuschäfer
Change-Id: I7a10a3fa5e1e9140a558f61109d0c9094d46e521 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-22soc/intel/skylake: Calculate soc reserved memory sizeSubrata Banik
This patch implements soc override function to calculate reserve memory size (PRMRR, TraceHub, PTT etc). System memory should reserve those memory ranges. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of intel soc reserved ranges. Change-Id: I19583f7d18ca11c3a58eb61c927e5c3c3b65d2ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21540 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-22soc/intel/common: Add function to get soc reserved memory sizeSubrata Banik
This patch ensures to consider soc reserved memory size while allocating DRAM based resources. Change-Id: I587a9c1ea44f2dbf67099fef03d0ff92bc44f242 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/skylake: Use EBDA area to store cbmem_top addressSubrata Banik
This patch uses BIOS EBDA area to store relevent details like cbmem top during romstage after MRC init is done. Also provide provision to use the same EBDA data across various stages without reexecuting memory map algorithm. BRANCH=none BUG=b:63974384 TEST=Ensures HW based memmap algorithm is executing once in romstage and store required data into EBDA for other stage to avoid redundant calculation and get cbmem_top start from EBDA area. Change-Id: Ib1a674efa5ab3a4fc076fc93236edd911d28b398 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/common: Add intel common EBDA supportSubrata Banik
This patch provides EBDA library for soc usage. Change-Id: I8355a1dd528b111f1391e6d28a9b174edddc9ca0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/skylake: Refactor memory layout calculationSubrata Banik
This patch split entire memory layout calculation into two parts. 1. Generic memory layout 2. SoC specific reserve memory layout. usable memory start = TOLUD - Generic memory size - - soc specific reserve memory size. Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/skylake: add Kabylake Celeron base SKUGaggery Tsai
This patch adds the support for Kabylake Celeron base SKU with PCH ID 0x9d50. BRANCH=none BUG=b:65709679 TEST=Ensure coreboot could recognize the Kabylake Celeron base SKU and boot into OS. Change-Id: I9c6f7bf643e0dbeb132fb677fcff461244101a55 Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
2017-09-21soc/intel/apollolake: Make SCI configurableMario Scheithauer
The System Control Interrupt is routed per default to IRQ 9. Some mainboards use IRQ 9 for different purpose. Therefore it is necessary to make the SCI configurable on Apollo Lake. Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-21soc/intel/skylake: Add config for enabling LTR for PCIe Root portRizwan Qureshi
There are a lot errors reported by AER driver for root port 0. The erors are being caused by an unsupported request from the device to the upstream port. Enabling LTR on the root port stops these errors, it is because LTR is enabled on the device side but not on the root port and hence root port was logging the LTR messages from the device as unsupported. The PCIe base spec (v3.1a) section 6.18 also states that: LTR support is discovered and enabled through reporting and control registers described in Chapter 7. Software must not enable LTR in an Endpoint unless the Root Complex and all intermediate Switches indicate support for LTR. Note that it is not required that all Endpoints support LTR to permit enabling LTR in those Endpoints that do support it. When enabling the LTR mechanism in a hierarchy, devices closest to the Root Port must be enabled first. If an LTR Message is received at a Downstream Port that does not support LTR or if LTR is not enabled, the Message must be treated as an Unsupported Request. FSP has a UPD for enabling/disabling LTR on root port, use the same for configuring LTR on PCIe root ports. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-21soc/intel/cannonlake: Remove old soc_get_rtc_failed functionMartin Roth
In coreboot commit bcd0bdabed (soc/intel/cannonlake: add rtc failure checking), the function soc_get_rtc_failed was supposed to be moved, but the old function was not removed, causing a build error. BUG=b:63054105 Change-Id: I31c1966af413df3f5a5492a5dd891a6eb26a1fc4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20vboot: reset vbnv in cmos when cmos failure occursAaron Durbin
There's an occasional issue on machines which use CMOS for their vbnv storage. The machine that just powers up from complete G3 would have had their RTC rail not held up. The contents of vbnv in CMOS could pass the crc8 though the values could be bad. In order to fix this introduce two functions: 1. vbnv_init_cmos() 2. vbnv_cmos_failed() At the start of vboot the CMOS is queried for failure. If there is a failure indicated then the vbnv data is restored from flash backup or reset to known values when there is no flash backup. BUG=b:63054105 Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20soc/intel/braswell: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: Ic4bf99dc3a26fbc3bd508e484963b9298ef1b24b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20soc/intel/baytrail: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: I1d90cc557225ddbba1787bf95eae0de623af487e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20soc/intel/skylake: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: I88bf9bdba8c1f3a11bc8301869e3da9f033ec381 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21554 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20soc/intel/cannonlake: add rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. In addition actually provide soc_get_rtc_failed() which properly indicates to the common code that RTC failure did occur in the cmos_init() path. BUG=b:63054105 Change-Id: I9dcb9377c758b226ee7bcc572caf11b7b2095425 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20soc/intel/broadwell: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: Ia0a38f00d2a5c7270e24bdd35ecab7fbba1016d4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20soc/intel/apollolake: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: I1b02028a1830ff9b28b23da7a4a1fd343f329f0d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20soc/intel/cannonlake: Add PMC pci driversLijian Zhao
Add PMC pci driver on top of PMC common code, also include pmc init code reference from skylake. Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19soc/intel/cannonlake: Add PCIE IRQsBora Guvendik
Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19soc/intel/common/block: Add pci device id for CNL-YBora Guvendik
Change-Id: I2820a39a34a80d066ca5cb364f67dbde0203803e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16soc/intel/common: smm.h: Fix copyright yearJonathan Neuschäfer
Intel obviously didn't exist in 201 :-) Change-Id: I230d3b92ec6832fcea056fd3d099147002274d73 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16soc/intel/apollolake: Leave Hda enabled for GLKHannah Williams
Audio was disabled during initial stages, this patch enables back. It was disabled to unblock other validation tests. TEST=lspci lists audio controller Change-Id: I5d3872e86623763e20ee6464897f47792c731642 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/21529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15soc/intel/skylake: Move UNCORE PRMRR base and mask defines.Pratik Prajapati
UNCORE PRMRR BASE and MASK MSRs are not common, so move to SOC specific header file and rename the #define to start with MSR_* Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15soc/intel/common/sgx: use SOC specific API to get PRMRR base and maskPratik Prajapati
Use soc_get_uncore_prmmr_base_and_mask() API to get PRMRR base and mask. Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21246 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15soc/intel/common/sgx: Define and use soc_fill_sgx_param()Pratik Prajapati
To remove chip.h dependency from SGX common code - Create API soc_fill_sgx_param() and use it in sgx.c - Implement same API for skylake/kabylake - define sgx_param structure Also include intelblocks/sgx.h instead of soc/msr.h Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14src/soc/intel/cannonlake: Define USB configuration paramsPratik Prajapati
Define USB2, USB3 and Type-C configuration for CannonLake. Change-Id: I42243950366d672e886158eb1934350f47b4ff1f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14soc/intel/skylake: Implement UNCORE PRMRR get base and mask APIPratik Prajapati
Implement soc_get_uncore_prmmr_base_and_mask() API for SKL/KBL Change-Id: I880d3d88138809cdf030507877079cbea52a0d97 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14soc/intel/apollolake: Implement UNCORE PRMRR get base and mask APIPratik Prajapati
Implement soc_get_uncore_prmmr_base_and_mask() API for APL/GLK Change-Id: I57df1f0e8ff984f32de4efdc6ebd68be501b4799 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14intel/common/systemagent: Add API to get SOC specific PRMRR base and maskPratik Prajapati
Implement weak definition and SOC specific code would implement actual definition. Change-Id: I5e787a2603aaa475cb5c61558cc31ec0afcb4a8b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13soc/intel/cannonlake: Add serialio device configLijian Zhao
Add SerialIO device mode configuration, device mode definition mirrored from FSP. Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13soc/intel/cannonlake: Add ramstage uart debug supportLijian Zhao
Use fixed resources for LPSS uart devices for debugging purpose. BUG=NONE BRANCH=NONE TEST=Boot up with coreboot rom, without this changes, serial log will stop print anything during PCI resourcre setup as MMIO address of UART will be re-assigned. Change-Id: Ib773e01d5f5358f13297400075d6920793200b88 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13intel/common/acpi: Use UART_BASE_0_ADDR macro for LPSS UARTV Sowmya
This patch fixes the build issue by replacing UART_DEBUG_BASE_ADDRESS macro with UART_BASE_0_ADDR macro to configure LPSS UART base adress for ACPI debug prints. TEST= Build and boot soraka and fetch the ASL debug prints. Change-Id: Ib31174701c56c88829ae0e725b546b66ea1ed16d Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao
Basic ACPI support for CNL on top of common ACPI, which will establish a root of FADT table, fill MADT entry, create gnvs field, record wake status and convert device names into DSDT dev definitions. Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-11soc/intel/skylake: Fix SPI WP disable status checkRavi Sarawadi
Use SPI write protect disable bit from BIOS_CONTROL register to check write protect status. Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21449 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-04 11:37:38 +0000