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path: root/src/soc/intel
AgeCommit message (Expand)Author
2020-01-02soc/intel/bsw/gpio.h: Drop unused valuesAngel Pons
2020-01-02src: Remove unneeded 'include <arch/io.h>'Elyes HAOUAS
2019-12-31soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADTMeera Ravindranath
2019-12-27arch/x86: Remove <arch/cbfs.h>Kyösti Mälkki
2019-12-26soc/broadwell/minihd: correct vendor, subsystem IDsMatt DeVillier
2019-12-26soc/intel/cannonlake: Move GPIO PM configuration to soc levelEric Lai
2019-12-26src: Remove unused include <string.h>Elyes HAOUAS
2019-12-26soc/intel/cannonlake: Clean up report_cpu_info() functionUsha P
2019-12-26soc/intel/cannonlake: Refactor pch_early_init() codeUsha P
2019-12-26soc/intel/skylake: Rename pch_init() codeUsha P
2019-12-25soc/intel/skylake/vr_config: Use lookup table by defaultPatrick Rudolph
2019-12-20soc/intel/tigerlake: Update FSP stack and heap sizeMaulik V Vaghela
2019-12-20{drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoCWim Vervoorn
2019-12-20{nb,soc}: Replace min/max() with MIN/MAX()Elyes HAOUAS
2019-12-19arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHEKyösti Mälkki
2019-12-19{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn
2019-12-19soc/intel/tigerlake: Add required header files in pch.cAamir Bohra
2019-12-19src: Remove unused 'include <arch/cpu.h>'Elyes HAOUAS
2019-12-19src/soc/intel: Remove unused <stdlib.h>Elyes HAOUAS
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
2019-12-19src: Remove unused include <device/smbus_def.h>Elyes HAOUAS
2019-12-18src: Remove unused 'include <bootblock_common.h>'Elyes HAOUAS
2019-12-17soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MBWim Vervoorn
2019-12-17soc/intel/skylake: Add irq 11 to the LNK* _PRSWim Vervoorn
2019-12-17soc/intel/apollolake: add support for extracting LBP2 from IFWIJeremy Compostella
2019-12-17soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash rangeWim Vervoorn
2019-12-17src: Conditionally include TEVTFrans Hendriks
2019-12-16src/soc/intel/cannonlake: Bump MAX_CPU from 8->12Edward O'Callaghan
2019-12-16soc/intel/tigerlake: Add FSP header and Fsp.fd file path for Jasper LakeAamir Bohra
2019-12-163rdparty/fsp: Update to current master againNico Huber
2019-12-16soc/intel/common/block/chip/Kconfig: Fix minor whitespaceHimanshu Sahdev aka CunningLearner
2019-12-16soc/intel/tigerlake: Pick correct pmc base reg from pch typeMaulik V Vaghela
2019-12-14Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"Nico Huber
2019-12-14bootblock: Provide some common prototypesKyösti Mälkki
2019-12-13soc/intel/common: Add PCI device IDs for CMP-HGaggery Tsai
2019-12-12soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.hFurquan Shaikh
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
2019-12-11soc/intel/tigerlake: Include soc common lpss header fileAamir Bohra
2019-12-11soc/intel/tigerlake: add soc implementation for ETR address APIAamir Bohra
2019-12-11soc/intel/Kconfig: Load Tiger Lake SOC KconfigAamir Bohra
2019-12-10soc/intel/common: Add Jasperlake Device IDsrkanabar
2019-12-10include/device/pci_ids: Add Coffeelake U IGD P630Christian Walter
2019-12-093rdparts/fsp: Update fsp submoduleJohanna Schander
2019-12-09soc/intel/bsw/gpio: Factor out GPI macrosAngel Pons
2019-12-06soc/intel/skylake: Add option to control microcode update inclusionWim Vervoorn
2019-12-05soc/intel/braswell: Use common sb code for SPI lockdown configurationArthur Heymans
2019-12-03src: Add missing include <stdlib.h>Elyes HAOUAS
2019-12-03soc/intel/cannonlake: Configure GPIO PM configuration in bootblockSubrata Banik
2019-12-03soc/intel/common/cse: Update comment for post-CAR global worldPatrick Georgi
2019-12-02soc/intel/cannonlake: Add gfx.asl fileMathew King