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2019-08-15cpu/x86/smm: Promote smm_memory_map()Kyösti Mälkki
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15arch/x86: Add postcar_frame_common_mtrrs()Kyösti Mälkki
As most platforms will share the subset of enabling both low RAM WB and high ROM WP MTRRs, provide them with a single function. Add possibility for the platform to skip these if required. Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/intel: Refactor platform_enter_postcar()Kyösti Mälkki
There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-15intel/denverton_ns: Drop unused save_gpio_routeKyösti Mälkki
Change-Id: I58131d77ba23024cd23e38584f8062d330d2564f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15cpu/x86/smm: Define single smm_subregion()Kyösti Mälkki
At the moment we only have two splitting of TSEG, one with and one without IED. They can all use same implementation. Make configuration problems of TSEG region assertion failures. Rename file from stage_cache.c to tseg_region.c to reflect it's purpose. Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-14soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory informationAndrey Petrov
Add code to read SPD data, parse it and save into SMBIOS table. This is implemented for socketed DDR4 chips only. For soldered-down memory this is not implemented and probably won't be ever needed. TEST=tested on OCP Monolake mainboard, and found dmidecode -t memory to work. The stack has also been tested on an out-of-tree board. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-08-14soc/fsp_broadwell_de: Implement SMBus read/write over IMCAndrey Petrov
Add read/write functions to hook it up with existing SPD retrieval code. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I9f5993dc795badf72751a4e6c9d974119a653e30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34679 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-14common/block/imc: Add Integrated Memory Controller (IMC) driverAndrey Petrov
IMC is found on certain Xeon processors. On such platforms SPDs are not connected to SMBus on PCH but to dedicated IMC-owned pins. The purpose of this driver is to expose access to the i2c/smbus controller associated with IMC. Datasheet used: Intel Xeon Processor D-1500 Product Family, Volume 2, reference 332051-001 This driver is largely based on i2c-imc.c Linux driver. https://lwn.net/Articles/685475/ TEST=single/double reads and single writes on Xeon-D1500. Hardware: Open Compute Project Monolake platform. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Idbcda1c2273b9a5721fcd9470b4de182192779e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34678 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13soc/intel/fsp_broadwell_de: Enable early integrated UARTAndrey Petrov
In order to use internal UART it needs to 'enabled'. This is normally done by FSP. However sometimes internal UART is needed before FSP is invoked. TEST=check if printk() show up in early romstage. Tested on OCP Monolake. Tested on out-of-tree mainboard to see if UART on LPC still works. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I88a7b1a38abf9a09137f6dd75a5a9dee104daaca Reviewed-on: https://review.coreboot.org/c/coreboot/+/34683 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13cpu/x86: Separate save_state struct headersKyösti Mälkki
Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-12soc/intel/common: Fix typo mistake in cache_as_ram.SSubrata Banik
Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09cpu/x86/smm: Drop SMI handler address from structKyösti Mälkki
Change-Id: Ib925b11ba269e0f3a9a0a7550705bf2a6794c5b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-09soc/intel/common: Set power-failure-state via option tableNico Huber
Allow get_option() to override the Kconfig choice. Change-Id: Ie91b502a38d1a40a3dea3711b017b7a5b7edd2db Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber
Get rid of this function and its dangerous, weak implementation. Instead, call pmc_set_power_failure_state() directly from the SMI handler. Change-Id: I0718afc5db66447c93289643f9097a4257b10934 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/apl: Implement power-failure-state APINico Huber
Needed some Makefile changes to be able to compile for SMM. Change-Id: Ibf218b90088a45349c54f4b881e895bb852e88bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/{cnl,icl}: Use new power-failure-state APINico Huber
pmc_soc_restore_power_failure() is only called from SMM, so add `pmc.c` to the `smm` class. Once all platforms moved to the new API, it can be implemented in a central place, avoiding the weak- function trap. Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/intel/skylake: Use new power-failure-state APINico Huber
Also move pmc_soc_restore_power_failure() which was guarded twice to not be included in SMM, where the only call lives. Once all platforms moved to the new API, it can be implemented in a central place, avoi- ding the weak-function trap. Change-Id: Ie72753764ecd876e6cb999fa0074d1114ae5efcf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34725 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/intel/common: Implement power-failure-state handlingNico Huber
This is a consolidation of the respective feature in `soc/intel/*lake/`, including additional support for MAINBOARD_POWER_STATE_PREVIOUS. For the latter, firmware has to keep track of the `previous` state. The feature was already advertised in Kconfig long ago, but not implemented. SoC code has to call pmc_set_power_failure_state() at least once during boot and needs to implement pmc_soc_set_afterg3_en() for the actual register write. Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09soc/intel/common/gspi: Use GSPI bus id to map to the controllerKarthikeyan Ramasubramanian
Currently SPI bus id is used to map to the controller in order to set the controller state. In certain platforms SPI bus id might not be exactly the same as GSPI bus id. For example, in Intel platforms SPI bus id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the GSPI controller that is not enabled. Use the GSPI id bus so that the right controller is set to active state. This fixes the regression introduced by CB:34449 BUG=b:135941367 TEST=Boot to ChromeOS. Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-08soc/intel/{APL, BSW, SKL}: Remove unused CPU_ADDR_BITS kconfigSubrata Banik
This patch removes CONFIG_CPU_ADDR_BITS kconfig from soc/intel/<soc>/Kconfig as not getting used anymore. Change-Id: Ie7fa386c9c0aae19da1fbd09407494d9812247a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34768 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08soc/intel: Fix SMRAM base MSRKyösti Mälkki
Previous setting was correct but assumed SMI handler is always located at the beginning of TSEG. Break the assumption. Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Handle smm_subregion() failureKyösti Mälkki
The callers don't necessarily check return value of function. Make sure the parameters are not left uninitialised in that case. Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08arch/x86: Change smm_subregion() prototypeKyösti Mälkki
Do this to avoid some amount of explicit typecasting that would be required otherwise. Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-08arch/x86: Move TSEG_STAGE_CACHE implementationKyösti Mälkki
This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
Add explicit CBMEM_STAGE_CACHE option. Rename CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE. Platforms with SMM_TSEG=y always need to implement stage_cache_external_region(). It is allowed to return with a region of size 0 to effectively disable the cache. There are no provisions in Kconfig to degrade from TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE. As a security measure CBMEM_STAGE_CACHE default is changed to disabled. AGESA platforms without TSEG will experience slower S3 resume speed unless they explicitly select the option. Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-08fsp_baytrail/fsp_broadwell_de: Sort entries in Makefile.inchcl-coreboot
Change-Id: I12e6ec4aec7dcadcbb886c3fc4c3b9126a0a835c Signed-off-by: Sourabh Kashyap <sourabhka@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-07intel/braswell: Drop config IED_REGION_SIZEKyösti Mälkki
Platform does not set up IED. Change-Id: Ied72888c6406b59332bc3d68eccb50bf1eab3419 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07intel/apollolake: Replace smm_region_info() with smm_region()Kyösti Mälkki
Implementation remains the same. Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07intel/icelake,skylake,cannonlake: Drop unused parameterKyösti Mälkki
Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07soc/intel: Obsolete mmap_region_granularity()Kyösti Mälkki
Change-Id: I471598d3ce61b70e35adba3bd983f5d823ba3816 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-06soc/*: Report mp_init errorsPatrick Rudolph
* Increase log level from ERR to CRITICAL in run_ap_work(). * Print or return errors if mp_run_on_all_cpus() failed. Tested on Supermicro X11SSH-TF. Change-Id: I740505e3b6a46ebb3311d0e6b9669e7f929f9ab9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-05soc/intel/{cnl,icl}: Add support to get LPSS controllers list from SOCAamir Bohra
This implementation adds support to provide list of LPSS controllers for a canonlake and icelake platforms. It implements strong function of get_soc_lpss_controllers defined under intel common block lpss driver. Change-Id: I36c87e2324caf8ed3e4bb3e3dc6f5d4edf3e8d46 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-05soc/intel/common/lpss: Add function to check for a LPSS controllerAamir Bohra
Add an API to check if device is a LPSS controller. This API can be used for IRQ assignments for LPSS PCI controllers, since the LPSS controllers have a requirement of unique IRQ assignments and do not share same IRQ# with other LPSS controllers. SOC code is reponsible to provide list of the LPSS controllers supported and needs to implement soc_lpss_controllers_list API, in case it needs to use this common implementation. Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05soc/intel/cnl/graphics: Hook up libgfxinitNico Huber
Change-Id: Ic038adad6cf76867cd4a8626d4c49e17018389fd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-04soc/intel/common/block/uart: Update the UART PCI device referenceAamir Bohra
This implementation revises the UART PCI device reference in common UART driver. The SOC functions have been aligned to provide the UART PCI device reference using pcidev_path_on_root. The uart_get_device() return type is changed, and files in which it gets used are updated. Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-08-03intel/baytrail,broadwell: Move stage cache support functionKyösti Mälkki
Let garbage-collection take care of stage_cache_external_region() when it is not needed and move implementation to a suitable file already building for needed stages. Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabledAamir Bohra
Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-02soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usageSubrata Banik
This patch overrides EnableTcoTimer FSP UPD default value based on PmTimerDisabled coreboot devcietree config. BRANCH=none BUG=b:138152075 Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-02soc/intel/common/pch: Move thermal kconfig selection into common/pchSubrata Banik
This patch moves SOC_INTEL_COMMON_BLOCK_THERMAL selection from respective soc/intel/{skl/cnl/icl} to common/pch/Kconfig. Change-Id: I7c9c8a87cfc5cb4c2fa8b215e56cc35c1f0cce28 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34650 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/icelake: Make use of common thermal code for ICLSubrata Banik
This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/skylake: Make use of common thermal code for SKLSubrata Banik
This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-01soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registersDavid Wu
Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:138282962 TEST=Ensure that the Interrupt status & enable registers are reset during the boot-up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-31soc/intel/skl: Add C232 chipset and reorder IDsFelix Singer
This patch ... - adds the PCH ID for C232 chipset, - renames "Premium" chipset to "HM170" (because of same IDs), - reorders the Skylake-H PCH IDs ascending by hex values. Used documents: - Intel 332690-005EN Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlakeAamir Bohra
FSP v1263 for CML supports FSP to use coreboot stack. This change selects common stack config, that enables coreboot to support share stack with FSP. BUG=b:133398276 Change-Id: I4098a4374363ca6f3c86c396d097f9eabc9a28fe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34130 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/common/block/lpss: Correct the PCI device referenceAamir Bohra
The initial implementation was assigning the devfn as PCI device reference directly which was incorrect. Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-31soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ixSumeet Pawnikar
Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 04:54:52 +0000