| Age | Commit message (Expand) | Author |
|---|
| 2019-12-19 | src: Use '#include <smp/node.h>' when appropriate | Elyes HAOUAS |
| 2019-12-19 | src: Remove unused include <device/smbus_def.h> | Elyes HAOUAS |
| 2019-12-18 | src: Remove unused 'include <bootblock_common.h>' | Elyes HAOUAS |
| 2019-12-17 | soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB | Wim Vervoorn |
| 2019-12-17 | soc/intel/skylake: Add irq 11 to the LNK* _PRS | Wim Vervoorn |
| 2019-12-17 | soc/intel/apollolake: add support for extracting LBP2 from IFWI | Jeremy Compostella |
| 2019-12-17 | soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash range | Wim Vervoorn |
| 2019-12-17 | src: Conditionally include TEVT | Frans Hendriks |
| 2019-12-16 | src/soc/intel/cannonlake: Bump MAX_CPU from 8->12 | Edward O'Callaghan |
| 2019-12-16 | soc/intel/tigerlake: Add FSP header and Fsp.fd file path for Jasper Lake | Aamir Bohra |
| 2019-12-16 | 3rdparty/fsp: Update to current master again | Nico Huber |
| 2019-12-16 | soc/intel/common/block/chip/Kconfig: Fix minor whitespace | Himanshu Sahdev aka CunningLearner |
| 2019-12-16 | soc/intel/tigerlake: Pick correct pmc base reg from pch type | Maulik V Vaghela |
| 2019-12-14 | Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID" | Nico Huber |
| 2019-12-14 | bootblock: Provide some common prototypes | Kyösti Mälkki |
| 2019-12-13 | soc/intel/common: Add PCI device IDs for CMP-H | Gaggery Tsai |
| 2019-12-12 | soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h | Furquan Shaikh |
| 2019-12-11 | printf: Automatically prefix %p with 0x | Julius Werner |
| 2019-12-11 | soc/intel/tigerlake: Include soc common lpss header file | Aamir Bohra |
| 2019-12-11 | soc/intel/tigerlake: add soc implementation for ETR address API | Aamir Bohra |
| 2019-12-11 | soc/intel/Kconfig: Load Tiger Lake SOC Kconfig | Aamir Bohra |
| 2019-12-10 | soc/intel/common: Add Jasperlake Device IDs | rkanabar |
| 2019-12-10 | include/device/pci_ids: Add Coffeelake U IGD P630 | Christian Walter |
| 2019-12-09 | 3rdparts/fsp: Update fsp submodule | Johanna Schander |
| 2019-12-09 | soc/intel/bsw/gpio: Factor out GPI macros | Angel Pons |
| 2019-12-06 | soc/intel/skylake: Add option to control microcode update inclusion | Wim Vervoorn |
| 2019-12-05 | soc/intel/braswell: Use common sb code for SPI lockdown configuration | Arthur Heymans |
| 2019-12-03 | src: Add missing include <stdlib.h> | Elyes HAOUAS |
| 2019-12-03 | soc/intel/cannonlake: Configure GPIO PM configuration in bootblock | Subrata Banik |
| 2019-12-03 | soc/intel/common/cse: Update comment for post-CAR global world | Patrick Georgi |
| 2019-12-02 | soc/intel/cannonlake: Add gfx.asl file | Mathew King |
| 2019-12-02 | soc/intel: Intel graphics driver scans generic bus | Mathew King |
| 2019-12-02 | soc/intel/cannonlake: Fix compilation | Praveen Hodagatta Pranesh |
| 2019-12-02 | soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE | Maulik V Vaghela |
| 2019-12-02 | src/soc/intel: Add Cometlake-S and CMP-H skus | Gaggery Tsai |
| 2019-12-02 | src/: Remove g_ prefixes and _g suffixes from variables | Patrick Georgi |
| 2019-11-29 | {northbridge,soc,southbridge}: Don't use both of _ADR and _HID | Elyes HAOUAS |
| 2019-11-29 | soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCK | Arthur Heymans |
| 2019-11-29 | soc/intel/braswell: Don't reinitialize SPI after lockdown | Arthur Heymans |
| 2019-11-29 | soc/intel/braswell: Use sb/intel/common/spi.c | Arthur Heymans |
| 2019-11-28 | soc/intel/tigerlake: select correct chipset based on soc Kconfig | Maulik V Vaghela |
| 2019-11-28 | pci_ids: Update Intel Lewisburg SMBUS PCI ID | Jonathan Zhang |
| 2019-11-28 | soc/intel/skl: Drop FSP_CAR remnants | Nico Huber |
| 2019-11-27 | soc/intel/skylake: Clean up report_cpu_info() function | Usha P |
| 2019-11-27 | soc/intel/cannonlake: Disable USB2 PHY Power gating | Surendranath Gurivireddy |
| 2019-11-27 | soc/intel/tigerlake: Fix smm_relocation_params | Kyösti Mälkki |
| 2019-11-27 | soc/intel/baytrail: Don't reinitialize SPI after lockdown | Arthur Heymans |
| 2019-11-27 | soc/intel/baytrail: Use sb/intel/common/spi.c | Arthur Heymans |
| 2019-11-27 | soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot | Angel Pons |
| 2019-11-26 | soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T | Subrata Banik |
