coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-18	src: Remove unused 'include <lib.h>'	Elyes HAOUAS
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-18	broadwell: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/jasperlake: Add function to display ME firmware status info	Krishna Prasad Bhat
2020-05-18	soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override	Eric Lai
2020-05-18	skylake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/common/block/smbus: Use i2c read eeprom to speedup SPD read	Wim Vervoorn
2020-05-18	jasperlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-18	soc/intel/common: add processor power limits control support	Sumeet R Pawnikar
2020-05-18	soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method	John Zhao
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-17	soc/intel/common: Rename cse_is_hfs3_fw_sku_custom()	Sridhar Siricilla
2020-05-17	soc/intel/common/block/acpi: Mask lower 20 bits of TOLUD	Furquan Shaikh
2020-05-17	soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax	Furquan Shaikh
2020-05-15	soc/intel: Correct comment on HMRFPO_ENABLE HECI command	Sridhar Siricilla
2020-05-14	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh
2020-05-14	soc/intel: Always advertise MMIO window above 4G in ACPI tables	Furquan Shaikh
2020-05-14	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh
2020-05-13	lib/spd_bin: add get_spd_sn function	Jamie Chen
2020-05-13	src/mainboard: Remove unused 'include <stdlib.h>'	Elyes HAOUAS
2020-05-13	src: Remove unused '#include <stddef.h>'	Elyes HAOUAS
2020-05-13	src: Remove unused '#include <stdint.h>'	Elyes HAOUAS
2020-05-12	soc/intel/skylake: Add ability to set root port ASPM	Wim Vervoorn
2020-05-12	soc/intel/tigerlake: Correct IRQ interrupt	Wonkyu Kim
2020-05-12	device/pci_device: Extract pci_domain_set_resources from SOC	Raul E Rangel
2020-05-12	soc/intel/jasperlake: Remove deprecated UPDs	Ronak Kanabar
2020-05-12	soc/intel/jasperlake: Add SATA related UPDs configuration	Ronak Kanabar
2020-05-12	soc/intel/tigerlake: Control SATA and DMI power optimization	Shaunak Saha
2020-05-12	soc/intel/skl: Drop weak mainboard_memory_init_params	Angel Pons
2020-05-11	soc/intel/quark: Revamp file headers	Patrick Georgi
2020-05-11	treewide: Replace BSD-3-Clause and ISC headers with SPDX headers	Patrick Georgi
2020-05-11	treewide: split off license text, remove extra copyright notices	Patrick Georgi
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-11	soc/intel/skylake: Allow setting of PcieRpMaxPayload	Wim Vervoorn
2020-05-11	soc/intel/tigerlake: Update C-State info	Wonkyu Kim
2020-05-11	soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX	Michael Niewöhner
2020-05-11	soc/intel/jasperlake: Add ACPI device name for Storage controllers	Karthikeyan Ramasubramanian
2020-05-11	soc/intel/jasperlake: Enable end of post support in FSP	Aamir Bohra
2020-05-10	src: Replace remaining GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-05-09	vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()	Julius Werner
2020-05-08	{security,soc}/*/Kconfig: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-05-08	soc/intel: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-05-08	soc/intel/skl: Drop `acpi_mainboard_gnvs`	Angel Pons
2020-05-07	soc/intel/tigerlake: Add PMC to platform ACPI name entry	John Zhao
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
2020-05-06	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha
2020-05-06	soc/intel/tigerlake: Print HPR_CAUSE0 register	derek.huang
2020-05-05	soc/intel/jasperlake: Correct the EMMC PCR Port ID	Ronak Kanabar