| Age | Commit message (Expand) | Author |
|---|
| 2020-09-14 | soc/intel/xeon_sp/cpx: display FSP_PREV_BOOT_ERR_SRC_HOB | Jonathan Zhang |
| 2020-09-14 | soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB | Anil Kumar |
| 2020-09-14 | soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake | Shreesh Chhabbi |
| 2020-09-14 | soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode | Aamir Bohra |
| 2020-09-12 | soc/intel/common/block/*/Kconfig: Guard options with if-blocks | Angel Pons |
| 2020-09-12 | soc/intel/denverton_ns/uart_debug: include header for uart_platform_base | Felix Held |
| 2020-09-12 | include/console/uart: make index parameter unsigned | Felix Held |
| 2020-09-11 | soc/intel/tigerlake: Clean up systemagent.h | Subrata Banik |
| 2020-09-10 | soc/intel/alderlake: Rename pch_init() code | Subrata Banik |
| 2020-09-10 | soc/intel/tigerlake: Maintain consistent tab in iomap.h | Subrata Banik |
| 2020-09-09 | soc/intel/common/block/imc: Drop unused code | Angel Pons |
| 2020-09-09 | soc/intel/common/block/uart/Kconfig: Drop unused symbols | Angel Pons |
| 2020-09-09 | soc/intel/xeon_sp: Select CPU_INTEL_COMMON | Angel Pons |
| 2020-09-09 | soc/intel/cannonlake: Add PCIe ports on PCH-H | Patrick Rudolph |
| 2020-09-09 | apollolake: Define MAX_CPUS at SoC scope | Angel Pons |
| 2020-09-09 | geminilake: Factor out MAX_CPUS value | Angel Pons |
| 2020-09-09 | soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbol | Angel Pons |
| 2020-09-09 | vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332 | Subrata Banik |
| 2020-09-08 | pci_ids: Add Alder Lake DTT PCI IDs | Subrata Banik |
| 2020-09-08 | pci_ids: Add Alder Lake IPU PCI IDs | Subrata Banik |
| 2020-09-08 | soc/intel/baytrail: Add missing GSM size definitions | Angel Pons |
| 2020-09-08 | soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE' | Elyes HAOUAS |
| 2020-09-08 | soc/intel/tigerlake: Skip GPIO configuration from FSP | Srinidhi N Kaushik |
| 2020-09-08 | soc/intel/elkhartlake: Update SA & PM related definitions | Tan, Lean Sheng |
| 2020-09-08 | soc/intel/elkhartlake: Update PMC related register definitions | Tan, Lean Sheng |
| 2020-09-08 | soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs Table | Tan, Lean Sheng |
| 2020-09-08 | soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake | Tan, Lean Sheng |
| 2020-09-08 | soc/intel/elkhartlake: Do initial SoC commit till ramstage | Tan, Lean Sheng |
| 2020-09-08 | soc/intel/apollolake: Hook up ENABLE_VMX | Angel Pons |
| 2020-09-08 | soc/intel/apollolake: Select CPU_INTEL_COMMON | Angel Pons |
| 2020-09-08 | soc/intel/broadwell: Drop `gpu_panel_port_select` | Angel Pons |
| 2020-09-08 | soc/intel/tigerlake: Add SMRR Locking support | Tim Wawrzynczak |
| 2020-09-08 | soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP | Tim Wawrzynczak |
| 2020-09-06 | soc/intel/apl: Add panel power and backlight configuration | Nico Huber |
| 2020-09-06 | soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default | Michael Niewöhner |
| 2020-09-05 | soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock | Subrata Banik |
| 2020-09-04 | soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_CO... | Elyes HAOUAS |
| 2020-09-04 | soc/intel/cnl: Enable HECI3 depending on devicetree | Felix Singer |
| 2020-09-04 | soc/intel/tigerlake: Remove unused PID_SDX macro | Subrata Banik |
| 2020-09-03 | soc/intel/cnl: Allow using the remaining Comet Lake FSPs | Felix Singer |
| 2020-09-03 | 3rdparty/fsp: Update submodule pointer to current master | Felix Singer |
| 2020-09-03 | soc/intel/cnl: Add new Kconfig option which matches its FSPs name | Felix Singer |
| 2020-09-02 | soc/intel/tigerlake: Add mainboard hook for overriding SoC config | Jes Klinke |
| 2020-09-02 | soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE' | Elyes HAOUAS |
| 2020-09-02 | {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a) | Elyes HAOUAS |
| 2020-09-01 | {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent | Subrata Banik |
| 2020-08-31 | soc/intel/elkhartlake/romstage: Do initial SoC commit till romstage | Tan, Lean Sheng |
| 2020-08-31 | soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblock | Tan, Lean Sheng |
| 2020-08-29 | PCI IDs: Add PCI ID for CML DPTF/DTT PCI device | Edward O'Callaghan |
| 2020-08-28 | vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc | Jonathan Zhang |
