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These are the simple cbmem_find() cases. Also drop the redundant
error messages.
Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Provide CmdMirror option in chip.h so that it can control CmdMirror FSP
UPD via dev tree.
BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename function from xeon_sp_get_cpu_count()
to xeon_sp_get_socket_count().
This function returns CPU socket count, by getting it from the field
named as numCpus in FSP HOB.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ic96bdf4ab042ac15d43f9b636185627c63fbf8a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42439
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4)
are available for TGL-U. They are dependent upon the SKU of the CPU
that the mainboard is running on. Volteer is updated here to use these
new limits.
To accomplish this, the SoC chip config's power_limits_config member
was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE
macros. Just before power limits are applied, the correct set of them
is chosen from the array based on System Agent PCI ID. Therefore, a
TGL board should have two sets of power limits available in the
devicetree.
BUG=b:152639350
TEST=On a Volteer SKU4 (4-core), verified the following console output:
CPU PL1 = 15 Watts
CPU PL2 = 60 Watts
CPU PL4 = 105 Watts
Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Each IIO stack has a personality. Only when personality of a stack is
TYPE_UBOX_IIO, the stack has PCIe devices.
For example, for CPX-SP, the stack 3 has personality of TYPE_UBOX, it
does not have PCIe devices.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2f6bfdac4d1110dd95f1b3a72e2e51f70c79212b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42333
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add uncore devices, interrupt definition, gnvs to xSDT tables.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2fa9c26abc6aef2d255535c2abf8b6b67d26359f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40927
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add processor power limits control support to configure values for
jasperlake soc based platforms.
BRANCH=None
BUG=None
TEST=Built for dedede system
Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Program PCU (Power Control Unit) during chip_final(). This
is needed to allow ACPI power control related feature to work
in target OS.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I1f5b18d66b351acecdc7b3f515a552c36f08eb61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This change updates platform.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for volteer.
Change-Id: I248f5e9a1e3ba4f6426167f0406073252cc6513a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42506
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Old (!PARALLEL_MP) cpu bringup uses this as the first
control to do SMM relocation.
Change-Id: I4241120b00fac77f0491d37f05ba17763db1254e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Broadwell does not have any `TESGMB`, but it has a `TSEGMB`.
Change-Id: Id25030aa86f2312e261eceb8b78c3878e9e0ee04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Idfb89ceabac6b6906e31a3dbe9096d48ba680599
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds support for SW CM. Add Operating System Capabilities
(_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet
Protocol tunneling and enable PCIe tunneling as well. Remove Connect
Topology(CNTP) command because kernel driver directly works with SW CM
Thunderbolt firmware. Update _DSD method for USB4 support across XHCI
and PCIe root ports.
BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Rename dptf.asl to dptf_common.asl under soc/intel/common/acpi path
to avoid any kind of confusion with another dptf.asl file under
soc/intel/common/acpi/dptf path. Sometime it's confusing to have
two dptf.asl files just one directory apart.
BUG=None
BRANCH=None
TEST=Build and boot on volteer system
Change-Id: I23d93719e23c0b7659ccb23e5d0868f879bc162c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add unique new acpi device ids for dptf for Tiger Lake soc based platforms
and update volteer speficic dsdt.asl file accordingly. The Linux kernel
driver expects these new acpi device ids for dptf functionalities.
BUG=None
BRANCH=None
TEST=Build and boot on volteer system
Change-Id: I7dbb812c0fc0f5084c98cf2752ce7ddce8e4d50e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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For baytrail and braswell, explicitly initialise
it to ACTIVE_ECFW_RO without ChromeEC.
For broadwell and skylake, fix it to report actual
google_ec_running_ro() status.
Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use LZ4 compression technique to compress FSP-S. This provides some
SPI ROM space savings (~36 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZ4 is chosen over LZMA since the decompression saves
~25 ms for an extra overhead of ~1KiB.
LZ4 Compression:
fsps.bin 0xe6fc0 fsp 254262 LZ4 (290816 decompressed)
LZ4 Decompression:
17:starting LZ4 decompress (ignore for x86) 712,361 (1,072)
18:finished LZ4 decompress (ignore for x86) 750,695 (38,334)
LZMA Compression:
fsps.bin 0xe6fc0 fsp 253415 LZMA (290816 decompressed)
LZMA Decompression:
15:starting LZMA decompress (ignore for x86) 707,696 (1,150)
16:finished LZMA decompress (ignore for x86) 767,763 (60,067)
BUG=b:158034451
TEST=Build and boot volteer mainboard.
Change-Id: I91e33eb7b688b5383f3a0075a28ac21250314973
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42444
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use LZ4 compression technique to compress FSP-S. This provides some
SPI ROM space savings(~60 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZ4 is chosen over LZMA since the decompression saves
~50 ms for an extra overhead of ~1.5 KiB.
LZ4 Compression:
fsps.bin 0xa9fc0 fsp 203423 LZ4 (262144 decompressed)
LZ4 Decompression:
17:starting LZ4 decompress (ignore for x86) 433,550 (1,154)
18:finished LZ4 decompress (ignore for x86) 461,620 (28,069)
LZMA Compression:
fsps.bin 0xa9fc0 fsp 202132 LZMA (262144 decompressed)
LZMA Decompression:
15:starting LZMA decompress (ignore for x86) 478,448 (1,174)
16:finished LZMA decompress (ignore for x86) 557,725 (79,277)
BUG=b:158034451
TEST=Build and boot waddledoo mainboard.
Change-Id: I416b1d91d7f4836b1e9c641b0fe07b39876364ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use LZMA compression technique to compress FSP-S. This provides some
SPI ROM space savings(~27 KiB) in each CBFS. FSP-M is XIP and hence not
compressed. LZMA is chosen over LZ4 since it provides extra space
savings of ~1 KiB for the decompression overhead of ~7 ms.
LZMA Compression:
fsps.bin 0xd1fc0 fsp 190132 LZMA (217088 decompressed)
LZMA Decompression:
15:starting LZMA decompress (ignore for x86) 343,289 (417)
16:finished LZMA decompress (ignore for x86) 373,922 (30,632)
LZ4 Compression:
fsps.bin 0xd1fc0 fsp 191310 LZ4 (217088 decompressed)
LZ4 Decompression:
17:starting LZ4 decompress (ignore for x86) 345,676 (581)
18:finished LZ4 decompress (ignore for x86) 369,101 (23,424)
BUG=b:158034451
TEST=Build and boot helios mainboard.
Change-Id: Ic0d0d81c81eaa365f3dbfdd2e00ac76cea287387
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42446
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove unused cannonlake dptf.asl file and cleanup defines from apollolake
dptf.asl file as per soc/intel/common/acpi code changes for dptf.
BUG=None
BRANCH=None
TEST=Build and boot on the system
Change-Id: I4c8bf2bd5da9d5881e7690bff34816b19dd96072
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Make dptf acpi device ids configurable for thermal functionality
as per soc/intel/common/acpi code changes for dptf.
BUG=None
BRANCH=None
TEST=Build and boot on volteer system
Change-Id: I5161d19dc663cdb9a7b004bb681059c9af2aaf4f
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Fix last legacy ASL syntax match in acpi/pcr.asl
BUG=none
TEST=Deltan coreboot binary remains the same after the changes are
applied
Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: Ia1021851b42b8fad52b3197d9003056d3dd2db04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42437
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support for enabling/disabling PCIe hot-plug via
a chip config option PcieRpHotPlug, which is copied to the corresponding
FSP-S UPD.
BUG=b:156879564
BRANCH=none
TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add CFL defaults for VR TDC config and provide Iccmax for additional Xeon
CPUs tested on the Prodrive/Hermes board.
Based on the following Intel documents:
* Document Number 570805 (XEON E EDS Vol 1)
* Document Number 337344 (CFL Datasheet Vol 1)
* Document Number 571264 (CFL CNP PDG)
Change-Id: I681de076318fb647c44cc8b8c42eb297018cc540
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This makes future changes easier to review.
Change-Id: I5d67801a46a1613fbc7f813e94933fa30c1b92df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Followups will remove remaining cases of PRMRR_SUPPORTED and
SMRR_SUPPORTED in the tree.
Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There are no side-effects in calling acpi_is_wakeup_s3()
and apm_control() is a no-op with HAVE_SMI_HANDLER=n.
Change-Id: Ia9195781955cc5fa96d0690aa7735fc590e527e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41986
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Attempts to write to APM_CNT IO port should always be guarded
with a test to verify SMI handler has been installed.
Immediate followup removes redundant HAVE_SMI_HANDLER tests.
Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The variable SETUP_XIP_CACHE provides us a working
alternative.
Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP_NV_STORAGE HOB is supported in CPX-SP FSP ww22 release.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ida06fa7f7c7937f4e66a83fdecbca8bc208d626f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42024
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since we plan to use VMX, enable CPU_INTEL_COMMON.
BUG=b:157388365
TEST=tested on Volteer
Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I5e7bdb4310947dd8a94ee554834a67ce94377ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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diff -ur src/soc/intel/skylake/acpi/pch_hda.asl src/soc/intel/cannonlake/acpi/pch_hda.asl
--- src/soc/intel/skylake/acpi/pch_hda.asl 2020-05-12 11:17:42.780293920 +0200
+++ src/soc/intel/cannonlake/acpi/pch_hda.asl 2020-05-12 11:17:42.756294169 +0200
@@ -4,7 +4,7 @@
Device (HDAS)
{
- Name (_ADR, 0x001F0003)
+ Name (_ADR, 0x001f0003)
Name (_DDN, "Audio Controller")
Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
Change-Id: Ic8b874163ddede72a75e0dc94021683bca3e7859
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Configure FSP-M UPD parameters.
TESTED=Boot CPX-SP based server.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I4d057a7c385ca563bfcc7ad44f651ad1f8ca003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Fix MADT table generation to keep IIO stack design in consideration.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Iec89551a8b88a683db5857e3a6ab4af5e446cb5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Add NUMA ACPI tables: SRAT, SLIT.
TESTED=Boot CPX-SP based server, check /sys/firmware/acpi/tables
for SRAT/SLIT tables.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I3374b802afd2d001e841afd85e7ae07bc27c01ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Modify soc/intel/common .asl files to comply with ASL2.0 syntax for
better code readability and clarity
BUG=none
BRANCH=none
TEST= Deltan coreboot binary remains the same after the changes are applied
Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: I8f95cf88f499d9f9bdd8c80c95af52f8fd886cdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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For Tiger Lake platforms, this patch set provides a way to override PCH
external VR settings and ext rail voltage/current through devicetree.
This enables setting of optimal settings for FIVRs for a particular PCH
type.
BUG=None
BRANCH=None
TEST=Build and boot volteer.
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ic55472d392f27d153656afbe8692be7e243bb374
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41424
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace 'cse_bp'(cse boot partition) and 'ME' with 'cse_lite' in all log
messages in the cse_lite.c.
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3fc677c9ec1962199c91cc310d7695dded4e0ba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41972
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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From `Documentation/coding_style.md`:
> This does not apply if only one branch of a conditional statement is a
> single statement; in the latter case use braces in both branches:
Change-Id: I5672949e587a9c0e4efa01521a659e4c224085d0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Unify the file with the Cannon Lake version
`src/soc/intel/cannonlake/smmrelocate.c`. Now they are identical.
Change-Id: I8cae66038edb3966604c92597986839badd617c5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Unify the file with the Cannon Lake version
`src/soc/intel/cannonlake/smmrelocate.c`.
Change-Id: Id4815836e93081b61f4c09b8b3ed81199d3ff409
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change adds Hot-Plug and power management event handers(_L61 &
_L69) respectively for Thunderbolt in the GPE scope. The _L61 method
invokes sub-method HPEV to support Hot-Plug wake event from Thunderbolt
PCIe root ports. This method intercepts Presence Detect Changed
interrupt and make sure the L0s is disabled on empty slots. The _L69
method checks and clears root port's PME SCI status.
BUG=b:156435065
TEST=Verified multiple hot plug successfully with Lenovo dock.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Also remove default mb/*/fadt.c from Makefiles.
Change-Id: I6a2839c524f8311ec9a382a84066afc7d579eaca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41948
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Connect Topology Command(CNTP) is sent with default timeout value
(0x1388) along with FW CM. The CNTP is supposed to be skipped while
using SW CM. While transition from FW CM to SW CM, the default timeout
value could cause boot time delay up to ~10 seconds. Set this FSPS UPD
ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds
delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs
value. While FSP finds this UPD value being 0, FSP will skip sending CNTP.
BUG=b:155893566
TEST=Built image with SW CM Thunderbolt firmware and verified no
outstanding delay time while using FSP v3197 during boot to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42056
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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