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2019-09-05soc/intel/cannonlake: memory spd data debugEric Lai
Add printing SPD data for debug usage. BUG=b:139397313 BRANCH=N/A TEST=Tested the on Hatch and checked cbmem log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1e257a8ea6ff9c906267841819d2a4b62a9e0b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-03soc/skylake: do not rely on P2SB data to generate DRHDAngel Pons
The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, define them as macros and use these values directly to generate the DRHD. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-03soc/intel/common/timer: Fix cosmetic errors as per CB:35148 reviewSubrata Banik
BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: I341eec13d275504545511904db0acd23ad34e940 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35234 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-03soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensorsSumeet Pawnikar
Add fan based active cooling for TSR sensors temperature range. BUG=b:138966929 BRANCH=None TEST=Verified Fan control functionality for TSR sensors on Hatch. Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-02soc/intel/common/timer: Make TSC frequency calculation dynamicallySubrata Banik
tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02soc/skylake: prevent null pointer dereferencesAngel Pons
Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-02soc/intel/quark: Remove variable set but not usedElyes HAOUAS
Change-Id: I09292c2776309982cfb4d72012991bf7725b75fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32912 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02soc/intel/skylake: enable GMM in devicetreeMaxim Polyakov
Enables Gaussian Mixture Model (GMM) only if the corresponding pci device is enabled in the device tree Tested on Asrock H110M DVS motherboard Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-02security/intel: Add TXT infrastructurePatrick Rudolph
* Add Kconfig to enable TXT * Add possibility to add BIOS and SINIT ACMs * Set default BIOS ACM alignment * Increase FIT space if TXT is enabled The following commits depend on the basic Kconfig infrastructure. Intel TXT isn't supported until all following commits are merged. Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-08-30soc/intel/skl/acpi: add description for missing PCIe portsMaxim Polyakov
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, ACPI contains a description for only 12 ports. This patch adds ACPI code for missing ports [1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN [2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003 [3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30soc/intel/skylake: Remove duplicated PCI IdMaxim Polyakov
Removes PCI_DEVICE_ID_INTEL_SKL_ID_DT because this PCI Id duplicates PCI_DEVICE_ID_INTEL_SKL_ID_S_4 (0x191f) Change-Id: I028a22d6a42c040f5991a03def3e410f515c1c7f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30intel/quark: Use common romstage entryKyösti Mälkki
Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30intel/quark: Select NO_SMMKyösti Mälkki
SoC was unintentionally flagged with SMM_TSEG when default values were assigned. Change-Id: I83202316f41ead66c7f69cad68dafaeccd09df66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30intel/quark: Remove extra steps on entry to romstageKyösti Mälkki
Change-Id: I9297d5b4f7c8ed703fb8772739531cdd7d5ca5f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-29intel/fsp_broadwell_de: Move and rename smm_lock()Kyösti Mälkki
There will be inlined smm_lock() that would conflict with this special case. Change-Id: I6752cbcf4775f9c013f0b16033b40beb2c503f81 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34874 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29intel/fsp_broadwell_de: Use smm_subregion()Kyösti Mälkki
Tested on OCP/Wedge100s: No error is visible in console output, still boots to OS. Change-Id: I986bbe978d3f68693b2d4538ccbcc11cdbd23c6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34745 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functionsPatrick Rudolph
Implement sa_get_tseg_base and sa_get_tseg_size. Used by Intel TXT and the new SMM API. Tested on OCP/Wedge100S. Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-28intel/broadwell: Use smm_subregion()Kyösti Mälkki
Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34738 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/haswell,broadwell: Rename EMRR to PRMRRKyösti Mälkki
The MSRs were already named as PRMRR in broadwell, just mismatching with the rest of the code. All later devices use the names PRMRR and UNCORE_PRMRR for these MSRs. Reflect the name change in structures and local variables. Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/braswell: Use smm_subregion()Kyösti Mälkki
Change-Id: I4af661f68c158cbed591fe017d4bc25239bddd37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34758 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/fsp_baytrail: Use smm_subregion()Kyösti Mälkki
Change-Id: I4e9de9c7f5decd784d881e5a733e995522be5226 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28google/rambi,intel/baytrail: Simplified romstage flowKyösti Mälkki
Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28soc/intel: Move fill_postcar_frame to memmap.cKyösti Mälkki
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28soc/intel/cnl: Add CML IGD IDsMeera Ravindranath
BUG=b:139798422 TEST=Build and boot CMLRVP. Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-28soc/intel/common/block: Provide mmc.c for setting dll registersKane Chen
Currently, we don't have UPDs to set emmc settings per mainboard on CML. This code change is to create mmc.c to provide interface to override dll settings per mainboard. Notice: set_mmc_dll function will override the dll values in FSP. BUG=b:131401116 BRANCH=none TEST=Boot to OS and confirm the dll values have been overridden. Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383 Signed-off-by: Kane Chen <kane.chen@intel.com> Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-27intel/baytrail: Use smm_subregion()Kyösti Mälkki
Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34739 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27intel/baytrail: Reorganize romstage.cKyösti Mälkki
Done just for future review convenience. Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34910 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27soc/intel/fsp_broadwell_de: Add ACPI HPET tableJohnny Lin
Tested on Mono Lake TEST=Note the kernel log: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 14.318180 MHz counter Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35027 Reviewed-by: Johnny Lin Reviewed-by: Andrey Petrov <anpetrov@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c codeSubrata Banik
This patch includes common romstage code to setup the console and load postcar. Fix booting regression issue on all latest IA-SOC introduced by CB:34893 Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-26intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki
This timestamp also got unintentionally removed from some boards as they were transformed to use common romstage entry. Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26soc/intel/cannonlake: Add config to disable display audio codecAamir Bohra
FSP 1263 looks for UPD configuration of "AudioLinkHda" if false it disables SDI# link for the codec. Change-Id: I8330f47416e580bf6b9ca1faed1de5cd578d0e2e Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35078 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21arch/x86: Rename some mainboard_romstage_entry()Kyösti Mälkki
These platforms use different signature for this function, so declare them with different name to make room in global namespace. Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21soc/intel/common/smm: Add missing printk statementTim Wawrzynczak
SMI trap handler was missing a printk statement, which caused Coverity to flag "data &= mask;" as a redundant operation. Change-Id: I71da74e5e08e7d7e6d61c1925db19324efd73f0a Found-by: Coverity CID 1381621 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-08-21soc/intel/common: use PAD_BUF() inside PAD_CFG_* macrosMaxim Polyakov
Use PAD_BUF() to disable the input/output buffer inside PAD_CFG_* macros instead PAD_CFG0_RX_DISABLE/PAD_CFG0_TX_DISABLE [1] https://review.coreboot.org/c/coreboot/+/34337 Change-Id: I19fd993e1f60d80eab0ce51eaed5e74ce1c6a34d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21soc/intel/common: gpio_defs: set trig to disable in PAD_NCMaxim Polyakov
There is no need to change the default value for the RX Level/Edge Configuration parameter if the pad is not used/connected (PAD_NC) Change-Id: Ie7eee83fba9320d52240166371fe0c757dbdce49 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21soc/intel/common: Set controller state to active in uart initUsha P
Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument "const struct device *dev" has been added to uart_lpss_init function. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML, ICL and APL platforms Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34810 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessorKyösti Mälkki
Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20soc/intel/cnl: Add provision to configure SD controller write protect pinAamir Bohra
Cometlake FSP allows provison to configure SD controller WP pin, As some of board design might choose not to use the SD WP pin from SD card controller. This implementation adds a config that allows to enable/disable SD controller WP pin configuration from FSP. BUG=b:123907904 Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34900 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20intel/apollolake: Move LPC decode enables to bootblockKyösti Mälkki
Doing this allows to call console_init() earlier in romstage. This also fixes IO UART in bootblock, although it appears there is currently no board that was affected. Change-Id: Iec363a8c651cc1b05b24229db09d686938118f3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34969 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20src: Remove variable length arraysJacob Garber
Variable length arrays were a feature added in C99 that allows the length of an array to be determined at runtime. Eg. int sum(size_t n) { int arr[n]; ... } This adds a small amount of runtime overhead, but is also very dangerous, since it allows use of an unlimited amount of stack memory, potentially leading to stack overflow. This is only worsened in coreboot, which often has very little stack space to begin with. Citing concerns like this, all instances of VLA's were recently removed from the Linux kernel. In the immortal words of Linus Torvalds [0], AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and much _slower_ code (and more fragile code), than just using a fixed key size would have done. [...] Anyway, some of these are definitely easy to just fix, and using VLA's is actively bad not just for security worries, but simply because VLA's are a really horribly bad idea in general in the kernel. This patch follows suit and zaps all VLA's in coreboot. Some of the existing VLA's are accidental ones, and all but one can be replaced with small fixed-size buffers. The single tricky exception is in the SPI controller interface, which will require a rewrite of old drivers to remove [1]. [0] https://lkml.org/lkml/2018/3/7/621 [1] https://ticket.coreboot.org/issues/217 Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20soc/intel/skylake/vr_config: Add loadline defaultsPatrick Rudolph
In addition to zero IccMax specified by mainboard with socketed CPU, allow a zero LoadLine default. The SoC code will fill in the default AC/DC LoadLine values are per datasheets: * "7th Generation Intel® Processor Families for H Platforms, Vol 1" Document Number: 335190-003 * "7th Generation Intel® Processor Families for S Platforms and Intel ®Core™ X-Series Processor Family, Vol 1" Document Number: 335195-003 The AC/DC LoadLine is CPU and board specific. TODO: Find out how to get the LoadLine from vendor firmware and find out how to map those to different CPU LoadLines. Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34938 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20soc/intel/skylake/vr_config: Add support for KBL-H and KBL-SPatrick Rudolph
Datasheets used: * "7th Generation Intel® Processor Families for H Platforms, Vol 1" Document Number: 335190-003 * "7th Generation Intel® Processor Families for S Platforms and Intel ®Core™ X-Series Processor Family, Vol 1" Document Number: 335195-003 This allows mainboards to specify a zero IccMax, which all mainboards with socketed CPU should do. Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34937 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20soc/intel/skylake/vr_config: Get rid of static lookup tablePatrick Rudolph
Use a switch case to find the correct VR config. The following commit will add more entries for which a lookup table isn't the best solution. Change-Id: Ib11c3d6e1eb339a0c7358c312a32731d835e7c73 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2019-08-20soc/intel/skylake/vr_config: Get rid of definesPatrick Rudolph
Get rid of defines and hardcode values directly. Just a cosmetic cleanup to make it more readable. Change-Id: I3eec44b38af356c3d87235740c65e2c2f6fc5876 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-20devicetree: Remove duplicate chip_ops declarationsKyösti Mälkki
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 01:45:07 +0000