coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-18	soc/intel,chromeos: Fix EC RO/RW status in GNVS	Kyösti Mälkki
2020-06-18	soc/intel/tigerlake: Enable FSP-S compression	Karthikeyan Ramasubramanian
2020-06-18	soc/intel/jasperlake: Enable FSP-S compression	Karthikeyan Ramasubramanian
2020-06-18	soc/intel/cannonlake: Enable FSP-S compression	Karthikeyan Ramasubramanian
2020-06-18	soc/intel: remove unused dptf.asl file and other defines	Sumeet R Pawnikar
2020-06-18	soc/intel/common: make dptf acpi device ids configurable	Sumeet R Pawnikar
2020-06-18	soc/intel/common: Introduce ASL2.0 syntax	Alexey Buyanov
2020-06-17	soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD	Wonkyu Kim
2020-06-17	soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimit	Patrick Rudolph
2020-06-17	soc/intel/cannonlake: Use table instead of switch-case	Patrick Rudolph
2020-06-16	cpu/x86: Define MTRR_CAP_PRMRR	Kyösti Mälkki
2020-06-16	sb,soc/intel: Replace smm_southbridge_enable_smi()	Kyösti Mälkki
2020-06-16	soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)	Kyösti Mälkki
2020-06-16	sb/intel: Remove spurious HAVE_SMI_HANDLER test	Kyösti Mälkki
2020-06-16	arch/x86: Create helper for APM_CNT SMI triggers	Kyösti Mälkki
2020-06-15	arch/x86: Remove NO_FIXED_XIP_ROM_SIZE	Kyösti Mälkki
2020-06-14	soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS	Jonathan Zhang
2020-06-14	soc/intel/tigerlake: enable CPU_INTEL_COMMON	Alex Levin
2020-06-14	soc/intel/cannonlake/acpi: Capitalize hex number to unify with Skylake	Paul Menzel
2020-06-14	soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add cpu entries in ssdt	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: fix MADT ACPI table	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add IIO stack resources to DSDT	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add NUMA ACPI tables	Jonathan Zhang
2020-06-13	soc/intel/common: Introduce ASL2.0 syntax	Alexey Buyanov
2020-06-12	soc/intel/tigerlake: Add devicetree support to change PCH VR settings	Venkata Krishna Nimmagadda
2020-06-10	soc/intel/common: Replace cse_bp and ME with cse_lite in all console logs	Sridhar Siricilla
2020-06-10	soc/intel/cannonlake: Put braces around else branch	Paul Menzel
2020-06-10	soc/intel/skylake: Remove space after type cast	Paul Menzel
2020-06-10	soc/intel/skylake: Use unit macros KiB and MiB	Paul Menzel
2020-06-10	soc/intel/tigerlake: Add Hot-Plug and PME event handlers for Thunderbolt	John Zhao
2020-06-10	ACPI: Remove Kconfig COMMON_FADT	Kyösti Mälkki
2020-06-09	soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs	John Zhao
2020-06-09	soc/intel/tigerlake: Increase heap size	Duncan Laurie
2020-06-08	spd/lp4x: Set manufacturer part name to blank (0x20)	Furquan Shaikh
2020-06-07	soc/intel/baytrail,braswell,broadwell,quark: Select COMMON_FADT	Kyösti Mälkki
2020-06-07	soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntax	Venkata Krishna Nimmagadda
2020-06-07	soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI device	Tim Wawrzynczak
2020-06-07	mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt()	Kyösti Mälkki
2020-06-07	acpi,soc/intel: Make soc/motherboard_fill_fadt() global	Kyösti Mälkki
2020-06-06	src: Use pci_dev_ops_pci where applicable	Angel Pons
2020-06-06	src: Remove unused 'include <cpu/x86/mtrr.h>'	Elyes HAOUAS
2020-06-06	src: Remove unused '#include <cpu/x86/smm.h>'	Elyes HAOUAS
2020-06-06	soc/intel/tigerlake: Add CPU ID for TGL B0	Jamie Ryu
2020-06-06	lp4x: Add new memory parts and generate SPDs	Furquan Shaikh
2020-06-06	soc/intel/jasperlake: Generate LP4x SPD files using gen_spd.go	Furquan Shaikh
2020-06-06	soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.go	Furquan Shaikh
2020-06-06	arch/x86: Declare permanent_smi_handler()	Kyösti Mälkki
2020-06-06	soc,southbridge/intel: Control SMI related FADT entries	Kyösti Mälkki
2020-06-06	soc/intel/xeon_sp/cpx: set up cpus	Jonathan Zhang