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path: root/src/soc/intel
AgeCommit message (Expand)Author
2019-09-13soc/intel/cannonlake: Allow coreboot to reserve stack for fspBora Guvendik
2019-09-12soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usageSubrata Banik
2019-09-12src/{northbridge,soc}: Remove not used #include <elog.h>Elyes HAOUAS
2019-09-12src/soc/intel/common/block/cse: Make hfsts1 common & add helper functionsSridhar Siricilla
2019-09-12soc/intel/cannonlake: Add config for sata devslp pad reset configurationAamir Bohra
2019-09-12soc/intel/{cnl, icl}: Cache the TSEG regionSubrata Banik
2019-09-12soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() APISubrata Banik
2019-09-11intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE KconfigSubrata Banik
2019-09-11soc/intel/common/block/cse: Move me_read_config32() to common codeSridhar Siricilla
2019-09-11arch/x86: Restrict use of _car_global[start|end]Kyösti Mälkki
2019-09-11arch/x86: Drop _car_relocatable_data symbolsKyösti Mälkki
2019-09-10soc/intel/skylake: Add option to toggle Hyper-ThreadingPatrick Rudolph
2019-09-09intel/fsp_broadwell_de: Add early timestampsKyösti Mälkki
2019-09-09intel/fsp_broadwell_de: Enable CONSOLE_CBMEM by defaultKyösti Mälkki
2019-09-09soc/intel/common/block/cse: Add helper function heci_send_receiveSridhar Siricilla
2019-09-09soc/intel/cannonlake: Allow coreboot to handle SPI lockdownSubrata Banik
2019-09-09soc/intel/cannonlake: Add ability to disable Heci1Bora Guvendik
2019-09-06soc/intel/skylake: Add Lewisburg family PCH supportMaxim Polyakov
2019-09-05soc/intel/cannonlake: memory spd data debugEric Lai
2019-09-03soc/skylake: do not rely on P2SB data to generate DRHDAngel Pons
2019-09-03soc/intel/common/timer: Fix cosmetic errors as per CB:35148 reviewSubrata Banik
2019-09-03soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensorsSumeet Pawnikar
2019-09-02soc/intel/common/timer: Make TSC frequency calculation dynamicallySubrata Banik
2019-09-02soc/skylake: prevent null pointer dereferencesAngel Pons
2019-09-02soc/intel/quark: Remove variable set but not usedElyes HAOUAS
2019-09-02soc/intel/skylake: enable GMM in devicetreeMaxim Polyakov
2019-09-02security/intel: Add TXT infrastructurePatrick Rudolph
2019-08-30soc/intel/skl/acpi: add description for missing PCIe portsMaxim Polyakov
2019-08-30soc/intel/skylake: Remove duplicated PCI IdMaxim Polyakov
2019-08-30intel/quark: Use common romstage entryKyösti Mälkki
2019-08-30intel/quark: Select NO_SMMKyösti Mälkki
2019-08-30intel/quark: Remove extra steps on entry to romstageKyösti Mälkki
2019-08-29intel/fsp_broadwell_de: Move and rename smm_lock()Kyösti Mälkki
2019-08-29intel/fsp_broadwell_de: Use smm_subregion()Kyösti Mälkki
2019-08-29soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functionsPatrick Rudolph
2019-08-28intel/broadwell: Use smm_subregion()Kyösti Mälkki
2019-08-28intel/haswell,broadwell: Rename EMRR to PRMRRKyösti Mälkki
2019-08-28intel/braswell: Use smm_subregion()Kyösti Mälkki
2019-08-28intel/fsp_baytrail: Use smm_subregion()Kyösti Mälkki
2019-08-28google/rambi,intel/baytrail: Simplified romstage flowKyösti Mälkki
2019-08-28soc/intel: Move fill_postcar_frame to memmap.cKyösti Mälkki
2019-08-28soc/intel/cnl: Add CML IGD IDsMeera Ravindranath
2019-08-28soc/intel/common/block: Provide mmc.c for setting dll registersKane Chen
2019-08-27intel/baytrail: Use smm_subregion()Kyösti Mälkki
2019-08-27intel/baytrail: Reorganize romstage.cKyösti Mälkki
2019-08-27soc/intel/fsp_broadwell_de: Add ACPI HPET tableJohnny Lin
2019-08-27soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c codeSubrata Banik
2019-08-26intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki