coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-07-14	src: Remove unused 'include <cpu/x86/msr.h>'	Elyes HAOUAS
2020-07-14	soc/intel/baytrail/northcluster.c: Add missing include	Elyes HAOUAS
2020-07-14	soc/intel/baytrail/romstage/pmc.c: Add missing include	Elyes HAOUAS
2020-07-14	soc/intel/baytrail/romstage/raminit.c: Add missing include	Elyes HAOUAS
2020-07-14	soc/intel/braswell/romstage/romstage.c: Add missing include	Elyes HAOUAS
2020-07-14	src: Remove unused 'include <stdint.h>	Elyes HAOUAS
2020-07-14	src: Remove unused 'include <types.h>'	Elyes HAOUAS
2020-07-12	soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controller	Mate Kukri
2020-07-12	soc/intel/gpio: Convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE()	Maxim Polyakov
2020-07-12	soc/intel/gpio: Convert PAD_CFG0_RX_POL_* to PAD_RX_POL()	Maxim Polyakov
2020-07-12	intel/gpio: Convert PAD_CFG0_TRIG_* to PAD_TRIG()	Maxim Polyakov
2020-07-12	soc/intel/common/block/pcie: Select ASPM on mainboard basis	Christian Walter
2020-07-12	soc/intel/xeon_sp/cpx: use HOB_TYPE_GUID_EXTENSION to interpret platform HOBs	Jonathan Zhang
2020-07-12	soc/intel/xeon_sp: Add RTC failure checking	Jingle Hsu
2020-07-12	vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt soc	Jonathan Zhang
2020-07-12	soc/intel/tigerlake: Move tco_configure to bootblock	Tim Wawrzynczak
2020-07-12	soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) device	John Zhao
2020-07-12	soc/intel/tigerlake: Add Type-C IOM base address and size macro	John Zhao
2020-07-12	soc/intel/tigerlake: Add new IGD device	Ravi Sarawadi
2020-07-09	soc/intel/broadwell/pcie.c: Drop dead code	Angel Pons
2020-07-09	soc/intel/baytrail/pmutil.c: Constify string arrays	Angel Pons
2020-07-09	soc/intel/baytrail/pmutil.c: Do not hardcode num_bits	Angel Pons
2020-07-09	soc/intel/baytrail: Align whitespace and comments	Angel Pons
2020-07-09	soc/intel/baytrail: Rename "pmc.h" to "pm.h"	Angel Pons
2020-07-09	mainboard/intel/tglrvp: Remove unused PrmrrSize chip config	Subrata Banik
2020-07-09	soc/intel/braswell: Drop some BIOS_SPEW printk's	Angel Pons
2020-07-09	soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND	Angel Pons
2020-07-07	soc/intel/common/block: Add new block DTT	Tim Wawrzynczak
2020-07-07	soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus master	John Zhao
2020-07-07	soc/intel/{tiger,jasper}lake: Add IPU to soc_acpi_name	Tim Wawrzynczak
2020-07-07	soc/intel/common: Add a minimal PCI driver for IPU	Tim Wawrzynczak
2020-07-07	lp4x: Add new memory parts and generate SPDs	David Wu
2020-07-06	src/**/acpi/smbus.asl: Drop dead code	Angel Pons
2020-07-06	soc/intel: Drop unused `#include <reg_script.h>`	Angel Pons
2020-07-06	soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init	Maulik V Vaghela
2020-07-04	soc/intel/xeon_sp/cpx: update HOB display code	Jonathan Zhang
2020-07-04	soc/intel/xeon_sp: Add read CPU PPIN MSR function	Johnny Lin
2020-07-04	soc/intel/tigerlake: Remove unused EHL DID from TGL SoC	Subrata Banik
2020-07-03	soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot	Jamie Ryu
2020-07-03	drivers/intel/pmx_mux: Remove redundant declaration	Kyösti Mälkki
2020-07-03	soc/intel/common: Only touch Time Window Tau bits in supported SoCs	Tim Wawrzynczak
2020-07-01	soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry	Jamie Ryu
2020-07-01	soc/intel/cannonlake: make satahotplug user configurable via devicetree	Jonas Loeffelholz
2020-07-01	soc/intel/common/cpu: Don't set any TCC settings if offset is 0	Tim Wawrzynczak
2020-07-01	soc/intel/skylake: Update ASL syntax in xhci.asl	Edward O'Callaghan
2020-07-01	soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4	John Zhao
2020-07-01	ACPI GNVS: Replace uses of smm_get_gnvs()	Kyösti Mälkki
2020-06-30	soc/intel/cannonlake: Add UWES ASL into xhci.asl	Edward O'Callaghan
2020-06-30	jasperlake: enable tcc_offset functionality	Sumeet R Pawnikar
2020-06-30	tigerlake: enable tcc_offset functionality	Sumeet R Pawnikar