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2017-07-14soc/intel/skylake: Set PsysPL2 MSRShelley Chen
BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-13soc/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-13soc/intel/cannonlake: Add reset.cAndrey Petrov
Add reset functionality. This implementation relies on CSE to trigger global reset. Change-Id: I7e6ae07a48f1cdc3d2f4cdb74246627d27253adf Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add MakefileAndrey Petrov
This enables building working bootblock and non-functional romstage and ramstage. Change-Id: I580cd2c3279d742f202b2adfbe55c814cfb48f99 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add bootblock PCHAndrey Petrov
Add essential initialization needed for PCH in bootblock. Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/cannonlake: Add early CPU initializationAndrey Petrov
Add basic CPU initialization for bootblock, as well as relevant headers. Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/skylake: reduce postcar stack usage for fsp 2.0Aaron Durbin
The FSP 2.0 path uses postcar to decompress ramstage. Since postcar is entirely RAM based there's no need to have an excessively large stack for the lzma decompression buffer. Therefore, reduce the stack required to 1 KiB like apollolake. Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/cannonlake: Add PCI dev macros and IDsAndrey Petrov
Change-Id: I287404f1615c6c0b441dd1b98a40e79919920a02 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12soc/intel/cannonlake: Add report_platform.cAndrey Petrov
Dump basic platform information early in bootblock. Change-Id: I12d1c9dd9f0518c133de465a4db72a0664a94eef Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20068 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-12soc/intel/skylake: Remove “disable SaGv” in recovery mode flowSubrata Banik
This reverts commit 5535cead (intel/skylake: Disable SaGv in recovery mode). Commit 5535cead disables SaGv in recovery mode to save few seconds booting time as we were doing memory training on every recovery flow. Now we don't need to perform MRC training on every recovery boot due to RECOVERY_MRC_CACHE implementation in place. Hence we don't need to define different SaGv policy between Normal (developer) mode and recovery mode to save few seconds. Using different SaGv parameters between recovery and all other mode has some significent drawbacks over warm reboot cycle. We are seeing a MRC traning hang in eve/soraka/poppy devices with below use case. Step 1: Boot system in developer mode (first time RW_MRC training) Step 2: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 3: System will perform recovery mode MRC training and boot to OS (first time RECOVERY_MRC training) Step 4: Issue “reboot” from OS console. Step 5: System wil boot in developer mode (using RW_MRC cache) Step 6: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 7: System will pick RECOVERY_MRC_CACHE and will hang during MRC training. This patch fixes issue mentioned above and ensures system boot to OS without any hang if we change mode (dev<->recovery) over warm reset. BUG=b:63515071 BRANCH=none TEST=manual stress testing of dev<->recovery mode over warm boot. No MRC hang with this fix on eve/soraka/poppy devices. Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-12Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"Subrata Banik
Don't need this additional 2ms delay as PCR read after sideband write help to fix original hard hang issue. This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e. Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/skylake: Perform PCR read after all PCR writeSubrata Banik
BIOS must ensure to read same PCR offset after PCR write operation is done. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<->D3 transition on eve failing unit. No hard hang with this fix. Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber
The PMC of PCH-H requires a different destination id. TEST=Run on kontron/bsl6 and observed that PM registers are correctly dumped at start of romstage. Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber
Move the generic I/O decode range setup before the console init. TEST=Run on kontron/bsl6 which requires 0xa80/0xa81 decoded to initialize serial ports. Serial console works from boot- block on. Change-Id: I9829f188c80eb73f6cd91b0c22e1c07da5745ad6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-10sgx: Move SGX code to intel/common/blockPratik Prajapati
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature is still enabled from devicetree.cb. As of now this SGX init supports only KBL (SKL not tested). Support of SGX for new SOCs would be added incrementally in this common code base. Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-03soc/intel/quark: Add I2C debuggingLee Leahy
Add I2C debugging support: * Add I2C_DEBUG Kconfig value to enable debugging * Display I2C segments before the transfer * Display errors that occur during the transfer * Display the number of bytes transferred for successful transfers TEST=Build and run on Galileo Gen2 Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-03soc/intel/apollolake: Use common gpio for apollolakeHannah Williams
No regression observed on a APL platform Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-02soc/intel/quark/spi.c: Explain a read in order to flush buffersMartin Kepplinger
In order for this (seemingly unnecessary) status assignment to stay, let's explain it in a comment. Change-Id: I0a364539c37005cfd637b75c8cc23b84e274294d Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-02soc/intel/cannonlake: Add bootblock.cAndrey Petrov
Change-Id: Ia951a466479b1e98e49895705162a66aece7609b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-02intel/block/cse: Add Cannon Lake SoC PCI device IDAndrey Petrov
Change-Id: Ida822d704b04cc4d1dfffb58003fc308bcb502d0 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-07-01soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignmentBarnali Sarkar
This patch basically does two things - 1) Remove unnecessary setting of flex_ratio to TDP nominal: Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured in MSR_PLATFORM_INFO(0xCE). If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done using MSR_FLEX_RATIO (0x194). Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is actually less than the factory configured Maximum Non TURBO Ratio (P1). So, this code is actually not required. Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor. This Bit implies Processor Boot Max Frequency - 0 = Disable Boot Max Frequency 1 = Enable Boot Max Frequency (Default) This setting determines if the processor will operate at maximum frequency at power-on and boot. Thus this patch will avoid one extra platform warm reset now onwards. 2) Remove wrongly setting Max Frequency in Bootblock phase: In the function set_max_frequency(), the P-State max ratio was set to TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non Trbo ratio. But, when the cpu gets reset, it will operate with the Max-Non Turbo ratio only, which is greater than the TDP Nominal ratio. So, no need to set back the ratio to TDP Nominal which is lower than the currently operating frequency. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/skylake/Kconfig: Drop useless FSP1.1/2.0 promptsNico Huber
There is no choice, if not leaving it with the default the build will fail. Change-Id: Id91e3ce87f8ced3001fcd2125f8f6781b270f5bc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/cannonlake: Add UART initializationAndrey Petrov
Cannonlake has built-in UART driver as part of LPSS block. However port mapped decoders are in use as well. Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin
When the C compiler expects 16-byte alignment of the stack it is at the call instruction. Correct existing call points from assembly to ensure the stacks are aligned to 16 bytes at the call instruction. Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-29soc/intel/common/block/gpio: Port gpio code from Apollolake to commonHannah Williams
Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/cannonlake: Add initial dummy directoryLijian Zhao
Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27soc/intel/common/opregion: Use enum cb_err as return valuePatrick Rudolph
Return CB_SUCCESS and CB_ERR instead of some integer. Preparation to merge intel/soc and intel/nb opregion implementations. Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/intel/quark: We're not Broadwell anymoreStefan Reinauer
... even though the author of the code probably wished he was working on a (much faster) broadwell system instead. Let's fix the header guard to reflect the right SOC. Noteworthy: clang detected that this was wrong. Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27soc/intel/skylake: storage: Use word access for power state registersDuncan Laurie
In the D0 and D3 ACPI methods use word access to the PME status and control register. This brings the code inline with the Intel reference code and matches how the kernel handles access to this register. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across multiple devices Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27soc/intel/skylake: storage: Add 2ms delay before exiting D3Duncan Laurie
For the skylake/kabylake generation of PCH there is an ACPI workaround for emmc/sd power state that involves disabling and re-enabling dynamic clock gating after enabling power to the controller, before setting the power state to D0. Under certain conditions we have observed that the controller is not powered and ready by the time the kernel attempts to read the PME control and status register and so the system will hang while attempting to read PCI config register 0x84. To ensure that the controller is ready add a 2ms delay after re-enabling dynamic clock gating and before setting the power state to D0. This issue has been observed on eMMC, but the same workaround exists for the SD card interface so the same delay is added there. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across many devices shows no hard hang after 2 days. Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-26soc/intel/fsp_baytrail/include/soc/pci_devs.h: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: I91ababb3bf7aa1ab0f71bb005c4685e81bb4d92f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-23soc/intel/skylake: Remove post SMM Relocation uCode loadingBarnali Sarkar
As per latest BWG, ucode reloading should be done at the end of Mp Init, i.e., after PRMRR and other features are enabled. No reloading specifically after SMM Relocation is required. As, in the Common CPU MP Init code, we are already doing a uCode load at the end of MP Init Feature Programming, hence, the uCode loading after SMM relocation can be removed. Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-23soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar
This patch uses the common CPU Mp Init code. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-23soc/intel/common/block: Add common MP Init codeBarnali Sarkar
This patch contains State Machine callbacks init_cpus() and post_cpu_init(). Also, it has the SOC call for CPU feature programming. Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20soc/intel/common: Add SMM common code for Intel PlatformsBrandon Breitenstein
SMI code is very similar across Intel platforms. Move this code to common/block/smi to allow it to be shared between platforms instead of duplicating the code for each platform. smihandler.h has already been made common so all it will contain is name changes and a move to the common block location. Due to moving smihandler code, APL changes are bundled here to show this change. Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/19392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-20soc/intel/quark: Add legacy SPI flash controller driverLee Leahy
Add SPI driver code for the legacy SPI flash controller. Enable erase and write support allowing coreboot to save non-volatile data into the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16soc/intel/skylake: Use SCS common codeBora Guvendik
This patch uses common SCS library to setup sd card. Change-Id: I06898e30a9b39f169b35f581a3ee09238f0f40c4 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/20217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16soc/intel/apollolake: Use SCS common codeBora Guvendik
This patch uses common SCS library to setup sd card. Change-Id: Iafbba04d7a498b9a321e8efee4abf07820d17330 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19632 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16soc/intel/common/block: Add Intel common SCS code supportBora Guvendik
Create Intel Common SCS code. This code currently only contains the code for SD card SSDT generation. More code will get added up in the subsequent phases. Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/19631 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16soc/intel/common/block/cse: Add GLK PCI IDHannah Williams
Change-Id: I88e376d61c4aba5030a0be7c8bdfe7b57881a197 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-16soc/intel/braswell: Hide some Kconfig options in menuconfigArthur Heymans
Don't allow the user to set PCIe configspace base address. Don't allow the user to set the DCACHE size and base. Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16soc/intel/skylake: Don't allow user to change DCACHE base and sizeArthur Heymans
Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16src/soc/intel: Don't allow user to select PCIe config mmio sizeArthur Heymans
Change-Id: I8b2794f56f39492589a08e5676cb33eec89a976e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20179 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16src/soc/intel/common: Don't allow user to change PCIe BARArthur Heymans
Change-Id: I254549057552be93611afa8ca52d22be220fe3dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16soc/intel/apollolake: Removing some menuconfig optionsArthur Heymans
Does not need to changeable in menuconfig. Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-15soc/intel/apollolake: revert CPU MP init prior to FSP-SAaron Durbin
A major regression was introduced with commit 6520e01a (soc/intel/apollolake: Perform CPU MP Init before FSP-S Init) where the APs execution context is taken away by FSP-S. It appears that FSP-S is not honoring the SkipMpInit UPD because it's been shown with some debug code that FSP-S is compeltely hijacking the APs: Chrome EC: Set WAKE mask to 0x00000000 Chrome EC: Set WAKE mask to 0x00000000 CBFS: 'VBOOT' located CBFS at [440000:524140) CBFS: Locating 'vbt.bin' CBFS: Found @ offset 2e700 size 1a00 Running FSPS in 4 secs.. 315875 4315875 cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work Running FSPS.. 4315875 4315875 ITSS IRQ Polarities Before: ITSS IRQ Polarities Before: IPC0: 0xffffeef8 IPC1: 0xffffffff IPC2: 0xffffffff IPC3: 0x00ffffff ITSS IRQ Polarities After: IPC0: 0xffffeef8 IPC1: 0x4a07ffff IPC2: 0x08000000 IPC3: 0x00a11000 This is essentially a revert of 6520e01a to fix the previous behavior. Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20215 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2017-06-14soc/intel/skylake: Add missing PCH_DEV_* definitionsFurquan Shaikh
Change-Id: Ib7aa495ccfd405d6ffc968388c28dc540da2f525 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-14soc/intel/common/block/i2c: Ignore disabled I2C devicesFurquan Shaikh
If I2C device is disabled: 1. BAR for the device will be 0 2. There is no need to generate ACPI tables for the device TEST=Verified that if an i2c device is disabled statically in devicetree or dynamically in mainboard, then coreboot does not die looking for missing resources. Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14soc/intel/skylake: Add USB port number information to wake sourceFurquan Shaikh
USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 12:45:40 +0000