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path: root/src/soc/nvidia/tegra124
AgeCommit message (Expand)Author
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
2015-04-04tegra124: use known-good drive for fast-train onlyNeil Chen
2015-04-04tegra124: add support for full DP link trainingNeil Chen
2015-04-03tegra124: implement platform_prog_run()Aaron Durbin
2015-04-02Nyans: replace cpu_reset with hard_resetDaisuke Nojiri
2015-03-31cbfs: remove cbfs_core.h includesAaron Durbin
2015-03-26tegra: Clean up USB codeFurquan Shaikh
2015-03-24vboot2: separate verstage from bootblockDaisuke Nojiri
2015-03-24nyans: reduce code duplication in bootblock and romstagesDaisuke Nojiri
2015-03-23vboot2: read secdata and nvdataDaisuke Nojiri
2015-03-21tegra124: switch to stopwatch APIAaron Durbin
2015-03-17coreboot classes: Add dynamic classes to corebootFurquan Shaikh
2015-03-13nyan: Remove broken setup_display() from romstageJulius Werner
2015-03-02coreboot arm: Define function for setting cntfrq registerFurquan Shaikh
2015-02-25tegra124: Clean up ARM UART driver buildMarc Jones
2015-02-17T124: perform ram_repair when CPU rail is powered on in warmbootYen Lin
2015-02-17T124: perform ram_repair when CPU rail is powered on in coldbootYen Lin
2015-02-17tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIMEJimmy Zhang
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2015-01-27vboot2: implement select_firmware for pre-romstage verificationDaisuke Nojiri
2015-01-27vboot2: add verstageStefan Reinauer
2015-01-14Revert "vboot2: add verstage"Paul Menzel
2015-01-13vboot2: add verstageDaisuke Nojiri
2015-01-09tegra124: fix and fine tune the warm boot codeJoseph Lo
2015-01-04tegra124: configure DP with correct pixel clockVince Hsu
2014-12-30i2c: Add software_i2c driver for I2C debugging and emulationJulius Werner
2014-12-30tegra124: Active dc/sor register change immediatelyVince Hsu
2014-12-30tegra124: display clock should be initialized before any accessVince Hsu
2014-12-26tegra124: Add a utility function to read the cause of the most recent reset.Gabe Black
2014-12-19nyan*: Add fast link training functionsJimmy Zhang
2014-12-17tegra124: modify panel init sequenceKen Chang
2014-12-17nyan*: enable CLAMP_INPUTSKen Chang
2014-12-17ARM: Use LPAE for Virtual Address TranslationDaisuke Nojiri
2014-12-17tegra124: change PLLD VCO calculation algorithmKen Chang
2014-12-16tegra124: Allow "best" PLLD parameters for unmatched pixel clock.Hung-Te Lin
2014-12-16tegra124: Always enable DC when attaching SOR.Hung-Te Lin
2014-12-16nyan*: debug: Add sor registers dump functionJimmy Zhang
2014-12-16tegra124: clock: Enforce PLL constraints for VCO and CFJulius Werner
2014-12-16nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 registerJimmy Zhang
2014-12-16nyan*: merge a couple of sor setting difference from kernel driverJimmy Zhang
2014-12-16nyan*: Apply sor fix from kernel dc driverJimmy Zhang
2014-12-16tegra124: Initialize display panel by EDID.Hung-Te Lin
2014-12-15tegra124: set MOT bit for I2C-over-AUXKen Chang
2014-12-15tegra124: Setup clock PLLD by approximating display panel pixel clock.Hung-Te Lin
2014-12-15tegra124: Release DMA channel at end of transactionDavid Hendricks
2014-12-15tegra124: Use correct mask for APB bus widthDavid Hendricks
2014-12-15nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.Gabe Black
2014-12-15tegra124: More improvements to the clock initialization macros.Gabe Black
2014-12-15tegra: spi: Read the command1 register to ensure the write to it completes.Gabe Black
2014-12-15tegra124: A couple clock fixes.Gabe Black
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