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path: root/src/soc/qualcomm/ipq806x/spi.c
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2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17qualcomm/ipq806x: add spi_crop_chunk()Patrick Georgi
That function requirement was added upstream but not in Chromium, so add an implementation. Change-Id: Ie384b315adb205586defa730b843c7c8e96f77fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10gpio: Extend common GPIO header, simplify function namesJulius Werner
We've had gpiolib.h which defines a few common GPIO access functions for a while, but it wasn't really complete. This patch adds the missing gpio_output() function, and also renames the unwieldy gpio_get_in_value() and gpio_set_out_value() to the much easier to handle gpio_get() and gpio_set(). The header is renamed to the simpler gpio.h while we're at it (there was never really anything "lib" about it, and it was presumably just chosen due to the IPQ806x include/ conflict problem that is now resolved). It also moves the definition of gpio_t into SoC-specific code, so that different implementations are free to encode their platform-specific GPIO parameters in those 4 bytes in the most convenient way (such as the rk3288 with a bitfield struct). Every SoC intending to use this common API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most 4 bytes in length. Files accessing the API only need to include <gpio.h> which may pull in additional things (like a gpio_t creation macro) from <soc/gpio.h> on its own. For now the API is still only used on non-x86 SoCs. Whether it makes sense to expand it to x86 as well should be separately evaluated at a later point (by someone who understands those systems better). Also, Exynos retains its old, incompatible GPIO API even though it would be a prime candidate, because it's currently just not worth the effort. BUG=None TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and Veyron_Pinky. Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08ipq806x: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns ipq806x to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Storm. Change-Id: Icb81a77e6f458625f5379a980e8760388dd3a1f9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bf23774c9ffa5d08c211f3658d39adcfa47b339 Original-Change-Id: I283cc7e6094be977d67ed4146f376cebcea6774a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224502 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9368 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23ipq806x: implement GPIO APIVadim Bendebury
Add implementation of the GPIO API defined in src/include/gpiolib.h. Also, clean up the GPIO driver, make it use pointers instead of integers for register address. This requires a touch in the SPI driver, where the CS GPIO is toggled and in the board function where it enables USB interface. BUG=chrome-os-partner:30489 TEST=tested with the following patches, observed proto0 properly read the board ID. Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210115 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2 Reviewed-on: http://review.coreboot.org/8718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-17ipq806x: Break apart large transfers in spi_xfer()David Hendricks
The current spi_xfer() function sets the count in hardware and then loops while waiting for the requested number of bytes to be sent or received. However, the number of bytes to be transferred may exceed the maximum count that can be programmed into the controller. This patch re-factors spi_xfer() to split the low-level FIFO handling portions for transmit/receive into their own functions to be called by loops in spi_xfer() which will break large transfers into smaller ones. BUG=chrome-os-partner:30904 BRANCH=storm TEST=built and booted with a >64KB payload on Storm Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209838 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108 Reviewed-on: http://review.coreboot.org/8676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04ipq806x: move GPIO definitions to the proper include fileVadim Bendebury
When the IPQ SPI driver was ported to coreboot, a few GPIO related definitions ended up in a wrong include file. Move them to the proper place and get rid of duplicated definition of GPIO_OUT. BUG=chrome-os-partner:27784, chrome-os-partner:29871 TEST=proto0 still boots with the new firmware Original-Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205328 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit df73bb0023f5eaf5594ef41b3632c4402ebf126c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I109e62e3bfc9bd15640ff697be7634f42435a3e4 Reviewed-on: http://review.coreboot.org/8058 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-31ipq8064: modify SPI controller driver to work in corebootVadim Bendebury
A typical SPI operation consists of two phases - command and data transfers. Command transfer is always from the host to the chip (i.e. is going in the 'write' direction), data transfer could be either read or write. We don't want the receive FIFO to be operating while the command phase is in progress. A simple way to keep the receive FIFO shut down is to not to enable it until the command phase is completed. Selective control of the receive FIFO allows to consolidate the receive and transmit functions in a single spi_xfer() function, as it happens in other SPI controller drivers. The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the next byte can be written or received, respectively. While data is being received the 0xFF bytes are transmitted per each received byte, to keep the SPI bus clocking. The data structure describing the three GSBI ports is moved from the .h file into .c file. A version of the clrsetbits macro is added to work with integer addresses instead of pointers. BUG=chrome-os-partner:27784 TEST=not yet, but with the res of the changes the bootblock loads and starts the rombase section successfully. Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197779 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f Reviewed-on: http://review.coreboot.org/7983 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-12-30ipq8064: copy u-boot spi driver as isVadim Bendebury
This brings in the banana_cs version of the SPI driver. BUG=chrome-os-partner:27784 TEST=none Original-Change-Id: Ie93ec8c962c26fff1f0a235516cd8a4062cab40b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194225 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3cada6e4ed51a6d4f637aa31a1a836352a99d13d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0a58a4ddaf9375c22c9b2b249a2baa2c5538ba6c Reviewed-on: http://review.coreboot.org/7982 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>