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2019-05-02sdm845: Add USB support on cheza platformChandana Kishori Chiluveru
This patch adds code to initialize two USB DWC3.0 controllers and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to initialize USB3.0 on the cheza mainboard. Synopsis controller initialization and configuration sequences taken from USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy programming. Includes Super speed mode support. TEST=USB keypad and mass-storage device enumeration tested with this patch Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02qualcomm: Add QCLib interface support to common/T Michael Turney
Change-Id: I38d086c379a3c2f54d1603a2fed5b33860f7f4d7 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-02sdm845: Select VBOOT_MIGRATE_WORKING_DATA, now requiredT Michael Turney
Change-Id: Idebbbd89de05d949e6f953aa49d8662d64383d1a Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-30vboot: refactor OPROM codeJoel Kitching
The name OPROM is somewhat inaccurate, since other steps to bring up display and graphics are needed depending on mainboard/SoC. This patch cleans up OPROM code nomenclature, and works towards the goal of deprecating vboot1: * Rename CONFIG_VBOOT_OPROM_MATTERS to CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig description * Remove function vboot_handoff_skip_display_init * Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY * Add |flags| field to vboot_working_data struct * Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild TEST=build and flash eve device; attempt loading dev/rec modes BRANCH=none Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-23soc/qualcomm/qcs405: add console.h includePatrick Georgi
Change-Id: I556d00e8b06f631a5ca51ae2b5ba646e5f536480 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32422 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23qcs405: Add support of GPIO IRQ APIsTaniya Das
Add support of GPIO IRQ APIs. Change-Id: I11715a93999012622a5e28455731cbe249ba8f2c Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23qcs405: clock: Update SPI APITaniya Das
Update SPI enable/disable and configure clock API for supporting all the blsp and qup for qcs405. Change-Id: I39622571cb671f62312283a010129ceecb654f61 Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-09src: Fix remaining #include <timer.h>Nico Huber
Follow-up to add76f91d5 (src: Use #include <timer.h> when appropriate). Change-Id: I7813daa0b73039ec76d33a16ce3ae0ce6cc7f2cc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-06src: Use #include <timer.h> when appropriateElyes HAOUAS
Also, extra-lines added or removed and local includes moved down. Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28qcs405: Add support for USB host modeVijayavardhan Vennapusa
Add required changes for USB host mode for USB disk enumeration. TEST=build & run Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Vijayavardhan Vennapusa <vvreddy@partner-android.googlesource.com> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-26qcs405: clock: Adding the clock support for qcs405Pranav Agrawal
Add basic clock support and enable UART, SPI clocks. Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Signed-off-by: Pranav Agrawal <pranava@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-26qcs405: Add GPIO APINitheesh Sekar
Introduce new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-21vboot: standardize on working data sizeJoel Kitching
Previously, the size of memory made for vboot_working_data through the macro VBOOT2_WORK was always specified in each individual memlayout file. However, there is effectively no reason to provide this customizability -- the workbuf size required for verifying firmware has never been more than 12K. (This could potentially increase in the future if key sizes or algorithms are changed, but this could be applied globally rather than for each individual platform.) This CL binds the VBOOT2_WORK macro to directly use the VB2_WORKBUF_RECOMMENDED_DATA_SIZE constant as defined by vboot API. Since the constant needs to be used in a linker script, we may not include the full vboot API, and must instead directly include the vb2_constants.h header. BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none CQ-DEPEND=CL:1504490 Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-18qcs405: Add DRAM resourcesNitheesh Sekar
TEST=build Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18qcs405: Add Timer supportNitheesh Sekar
Init frequency to 19.2 MHz TEST=build Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18soc/qualcomm/qcs405: Add MMU supportNitheesh Sekar
Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18soc/qualcomm/qcs405: Support for new SoCNitheesh Sekar
Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-14console: Change BOOTBLOCK_CONSOLE default to `y`Nico Huber
Invert the default instead of selecting it everywhere. Restores the ability to use its Kconfig prompt. Beside Qemu targets, the only platforms that didn't select it seem to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The latter two were about to be patched anyway. Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30891 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05sdm845: Add SPI-NOR flash driverMukesh Savaliya
TEST=build & run Change-Id: Ie404faf37617d2ad792310709ca2063f9a372076 Signed-off-by: Mukesh Savaliya <msavaliy@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/25392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-30sdm845: Add clock supportDavid Dai
This sets up initial clock configuration for QUP and QSPI, and includes configuration of Root Clock Generators(RCG) and clock branches enablement. TEST=build & run Change-Id: I0b1d7f6daa179c0b24a97d42b66c1a9ee596b0a3 Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/25454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-21(console,drivers/uart)/Kconfig: Fix dependenciesNico Huber
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16soc/qualcomm/ipq{40xx,806x}/Kconfig: Remove unused MBN_ENCAPSULATIONElyes HAOUAS
Change-Id: I4cf5cd1d3bed7188590e4f143d8f14dc9e58b183 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-07sdm845: Implement bitbang UART for bootblockJulius Werner
This patch replaces the UART in the bootblock of SDM845 with a bitbang implementation. Since SDM845 hardware UART needs a firmware blob loaded into it before it becomes usable, it is not really suited for use in the bootblock (since by the time we can read blobs from SPI, the bootblock is essentially over anyway). This solution allows us to still have some console output during early SoC initialization. Change-Id: I0c252ec83a7993edce5c4debc687f1fdd0d7b36d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-01sdm845: Add GPIO APIDavid Dai
Introduces new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I8cef9dae2072da32cb0678efefeb8f0070cdde9c Signed-off-by: David Dai <daidavid1@codeaurora.org> Reviewed-on: https://review.coreboot.org/26233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-22sdm845: increase SRAM for bootblockT Michael Turney
Bootblock has grown beyond 32K, grow to 40K Change-Id: Iedc52151e223ebf4ff5b35a419b5378a6f1c661b Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/26760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-29src/soc: Add and update license headersMartin Roth
This change adds and updates headers in all of the soc files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all soc directories. Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-28soc/qualcomm: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ib7bcfefaecc053a1ed28d708a614acb81207bccf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09sdm845: Add DRAM resourcesT Michael Turney
TEST=build Change-Id: Icf934caf8b4584ef2633054a5cc7f5be7cc734ee Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01sdm845: Add Timer supportT Michael Turney
Frequency set to 19.2 MHz TEST=build Change-Id: I56e57156df8a74cf629f7ada86cf5a5fcd5ad3c4 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-23soc{broadcom,imgtec,mediatek,qualcomm}: stop using spi_xfer_two_vectorsAaron Durbin
On a second look broadcom/cygnus and imgtec/pistachio appear to support full duplex. Therefore, remove the use of spi_xfer_two_vectors(). For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such a way that it does not support full duplex. Remove the use of spi_xfer_two_vectors() and explicitly error out when a full duplex transaction is requested. Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25742 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/qualcomm/sdm845: Add MMU supportT Michael Turney
Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM TEST=build Change-Id: Ic6cf022b08bb2568fdf956cea8bad46da89236c5 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25201 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/qualcomm/sdm845: remove hole in memlayout.ldT Michael Turney
Removed 33KB hole in SSRAM TEST=build & run Change-Id: I6851860f878d9a0688975fa855980870d657ee1a Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25391 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-09 06:43:07 +0000