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coreboot
2560p
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broadwell_refcode
e6230
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Some coreboot project code with my work
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rk3288
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Author
2015-06-26
rockchip/rk3288: complete vboot configuration and move to SoC
Patrick Georgi
2015-06-21
Remove old HAVE_UART_MEMORY_MAPPED select statements
Martin Roth
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-05-19
Remove Kconfig variable that has no effect
Patrick Georgi
2015-04-22
rtc: add config flag to denote rtc API availability
Patrick Georgi
2015-04-22
soc: select generic gpio lib on (almost) all non-x86 SOCs
Stefan Reinauer
2015-04-20
rk3288: Disable ramstage compression by default
Julius Werner
2015-04-15
veyron_*: Move PMIC_BUS to a Kconfig variable
David Hendricks
2015-04-14
CBFS: Automate ROM image layout and remove hardcoded offsets
Julius Werner
2015-04-10
rk3288: Adjust CBFS header and ROM offsets
Julius Werner
2015-04-08
timer: Add generic udelay() implementation
Aaron Durbin
2015-04-06
New mechanism to define SRAM/memory map with automatic bounds checking
Julius Werner
2015-04-02
rk3288/pinky: Move uart address to mainboard Kconfig
David Hendricks
2015-04-02
veyron: select rw romstage using vboot2
Daisuke Nojiri
2015-03-24
add make_idb.py & update bootblock
huang lin
2015-03-17
rockchip/rk3288: Fix whitespace
Kyösti Mälkki
2015-03-16
coreboot: rk3288: Add a stub implementation of the rk3288 SOC
jinkun.hong