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This patch passes the coreboot table base address to ARM TF on RK3399
devices to be able to use the new coreboot table parsing support.
Change-Id: I5cb2f13ce71e374207d0fa7a71c38852d680dc56
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23557
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The Rockchip UARTs are tied directly to the 24MHz oscillator and are
thus clocked with exactly 24MHz. The reasons why our code instead uses
some 23.xxMHz value have long been lost in time. For the current shared
8250 implementation, the baud rate divisor for 115200 would be the same.
Correcting this does make the information in the coreboot table more
accurate and help payloads chose a better divisor, though.
Change-Id: Ieceb07760178f8ddbb5936f8742b78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This header uses common types and macros so it needs to include the
headers that provide those itself.
Change-Id: Ieceb0deadbeef8ddbbb00b13542b78f8def4072d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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We found when ambient temperature low, with now saradc frequency and
delay between saradc power up and start command, there may get wrong
adc value, then get the wrong ramid or boardid, so lower the saradc frequency
and add the delay time between power up and start command.
BUG=b:70692504
BRANCH=gru
TEST=test on Dru in 0C temperature, always get right adc value
Change-Id: I42e49ca63299479912fa05e2a62cba6f2de4b337
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Some panels need to transfer initial code, and some of them will be
over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi
dsi transfer function to support it.
Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch fixes 2 edp display issues:
1. When rk_edp_prepare fails >3 times, edp_init isn't run because
while-condition is not satisfied. Then, only a partial init sequence is
ran. This causes all aux transactions to fail.
2. If rk_edp_prepare never succeeds, coreboot never leaves link training
stage due to infinite loop. Boot process is stuck.
TEST=Boot past eDP initialization stage and make sure AP logs don't have
show aux transaction fails.
Change-Id: I44c3f53e8786558c43078d4afe9acde4d64796e7
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/23152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Due to a schematic error, our code was written to configure more I2S0
pins than are actually used. We're also pinmuxing the whole bank of pins
over to the I2S controller even though we don't need them all. Restrict
the GPIO initialization and pinmuxing to the pins we really need so the
other ones can be correctly used as SKU ID pins on Scarlet.
Also, move the "audio" IO voltage domain selection to the other such
selections in the bootblock, since that covers two whole banks of GPIOs
and there's no guarantee that they're all used for audio (and thus not
needed before ramstage).
BUG=b:69373077
TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2.
Change-Id: I9314617e725fe83d254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
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This option should've been selected by RK3399 the whole time since the
SoC supports the <soc/gpio.h> interface. It wasn't really a big deal
until now where I'm trying to use a the base2 read helper, though.
Change-Id: Ib7a5f00a6680163105fc0598ce77d03f3645f05a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22744
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Support kd097d04 dual mipi panel on Scarlet.
Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Refactor the mipi driver, so we can support dual mipi panel.
And pass the panel data from mainboard.c, that we can
support different panel with different board.
Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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These values are specified as constant time periods but the PHY
configuration is in terms of the current lane byte clock so using
constant values guarantees that the timings will be outside the
specification with some display configurations.
Derive the necessary configuration from the byte clock in order to
ensure that the PHY configuration is correct.
Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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check GEN_CMD_FULL status before transfer, check
GEN_CMD_EMPTY and GEN_PLD_W_EMPTY status after
transfer.
Change-Id: I936c0d888b10f13141519f95ac7bcae3e15e95d9
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch correct Feedback divider setting:
1. Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must be greater than
12, less than 1000.
2. Make the previously configured Feedback divider(LSB)
factors effective
Change-Id: Ic7c5c59be1d00c65c3b17cb3c4bfba8d7459e960
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0>
should depend on frequency, so fix it.
Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Accroding to datasheet, feedback divider register high value is only
4 bit, it currently uses 5 bit, so correct it.
Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Allows explicit ordering for vendors that share a common configuration
that must be sourced last.
The issue is that chips in soc/{amd,intel}/[ab].* will be able to
override defaults set in this file, but Kconfig files that get sourced
later (soc/amd/[d-z].*) will NOT be able to override these defaults.
Note: intel and amd soc chips now need to be added manually to the new
Kconfig file
BUG=b:62235314
TEST=make lint-stable
Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
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struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
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struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
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-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
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-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
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-msg.read = 1;
+msg.flags = I2C_M_RD;
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-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
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-!!(msg.read)
+(msg.flags & I2C_M_RD)
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-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
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-msg->read = 1;
+msg->flags = I2C_M_RD;
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-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
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-!!(msg->read)
+(msg->flags & I2C_M_RD)
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-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Starting with RK3399, PMUGPIO pull registers use the same write mask
format as normal GRF registers, so they need to use RK_CLRSETBITS()
rather than clrsetbits_le32().
BRANCH=None
BUG=None
TEST=boot from scarlet
Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM
Trusted Firmware has since become a thing and chosen a slightly
different way to represent GPIOs in a 32-bit word. Let's align our
format to them so we don't need to remember to convert the values every
time we pass them through.
CQ-DEPEND=CL:572228
Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the coreboot DDR Settings to match the configuration
used by ARM-Trusted-Firmware.
Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The differential signal of DQS needs to keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it. But if it has PHY side ODT
connected at this time, it will change the DQS
signal level. So it needs to disable PHY side ODT
when doing gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f
Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448278
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user
option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to
use the latter in a choice.
Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch fix rk_mipi_dsi_phy_init error return.
Change-Id: Ie260975ad6ed26c37aa8bb65dfcef4db2407a2da
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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It seems that the BootROM on the RK3399 overwrites some of the earlier
parts of SRAM, including the PRERAM_CBMEM_CONSOLE area. Now that we have
a persistent CBMEM console we want that area to survive in case of an
early (pre-CBMEM) reboot, so shuffle the layout around a bit to move it
further back. (This reduces the stack size to 12KB which should still be
way more than enough.)
Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This is in preparation to get rid of the strong spi_setup_slave
implemented by different platforms.
BUG=b:38430839
Change-Id: I66b1b9635ece2381f62f2a9d6f5744d639d59163
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Reserve the whole TZRAM area because it will be marked as secure-only
by BL31 and can not be accessed by the non-secure kernel.
CQ-DEPEND=CL:452659
BUG=chrome-os-partner:57361
BRANCH=firmware-gru-8785.B
TEST=the reserve memory is resized
Change-Id: Ie3ab39598f3f7cb96feb0c574e230e7fcb53a1a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f34d254e1dfc9ae95a784aba22503e75a2fa65f1
Original-Change-Id: I39c4cb530f41a7b0f7f3064125072dd85b62276f
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/418102
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-(cherry picked from commit ea9fe064a9b1e1ce81fca74f829a0fb6e78ce426)
Original-Reviewed-on: https://chromium-review.googlesource.com/452640
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This patch configures clock for mipi and then
adds mipi driver for support innolux-p079zca
mipi panel in rk3399 scarlet.
Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The hang was caused by deasserting the reset before, it had been delayed 20us
fixing the hang issue.
So we can remove this delay for now.
Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations’ Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
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Board Scarlet doesn't use usbphy1.
BUG=b:37685249
TEST=boot Scarlet, check the firmware log, and confirm
no errors about USB1
Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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BUG=b:35647967
TEST=boot from bob
Change-Id: I5de902ab26fe768b641f69d85a5294baf6d916e3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 223257d486b026c06a1f3a7a830b829efb9932dc
Original-Change-Id: I055ad5f59285cee3110d1e7cb1a53a60144712e4
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/452285
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19433
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are
linked directly into the bootblock or the romstage. However, they're
still compiled with a separate "libverstage" source file class, linked
into an intermediate library and then linked into the final destination
stage.
There is no obvious benefit to doing it this way and it's unclear why it
was chosen in the first place... there are, however, obvious
disadvantages: it can result in code that is used by both libverstage
and the host stage to occur twice in the output binary. It also means
that libverstage files have their separate compiler flags that are not
necessarily aligned with the host stage, which can lead to weird effects
like <rules.h> macros not being set the way you would expect. In fact,
VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86
because their libverstage code that gets compiled into the romstage sets
ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to
run pre-migration.
This patch resolves these problems by removing the separate library.
There is no more difference between the 'verstage' and 'libverstage'
classes, and the source files added to them are just treated the same
way a bootblock or romstage source files in configurations where the
verstage is linked into either of these respective stages (allowing for
the normal object code deduplication and causing those files to be
compiled with the same flags as the host stage's files).
Tested this whole series by booting a Kevin, an Elm (both with and
without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode.
Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18302
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It may cause an edp aux transfer error if the edp pclk is
set too high, so reduce it to 25MHz.
BUG=chrome-os-partner:60130
BRANCH=None
TEST=Build and Boot
Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596
Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/429410
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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After we set the GET_TIME bit, the rtc time can't be read immediately. We
should wait up to 31.25 us, about one cycle of 32khz. Otherwise reading
RTC time will return a old time.
BUG=chrome-os-partner:61078
BRANCH=veyron
TEST=Build and Boot
Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/423272
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9806b624d6e968e51d52aab8c052ae3fa77f247d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4b708e29fbae0d8f5a2cece79711aa6b1887727
Original-Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/427522
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18127
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Updated to arm-trusted-firmware TOT:
236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size)
183 commits between Sep 20, 2016 and January 10, 2017
- Also add associated change to src/soc/rockship/rk3399 Makefile.inc
that is required to build the M0 Firmware.
Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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I've recently added an assertion to ensure that the effective I2C
frequency on Rockchip SoCs is not too far off the 400KHz target due to
divisor rounding errors. A 10KHz margin worked fine for RK3399, but it
turns out that RK3288 actually only ever hit 387KHz since its I2C clocks
are based off the already pretty low 75MHz PCLKs. While we could
probably change the PCLKs to make this closer, that seems like a too
intrusive change for something that has already worked just fine for
years, so just loosen the restriction a little more instead.
BRANCH=None
BUG=chromium:675043
TEST=None
Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421095
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/18007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could
improve stability like kernel.
CQ-DEPEND=CL:386527
BUG=chrome-os-partner:54377
BRANCH=none
TEST=build and boot on kevin
Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6eb1f56371aea51f2584a97bf817189d61090b2
Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1
Original-Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386865
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17790
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We may support different sdram sizes on one board in future, so
we need to calculate sdram sizes from sdram drvier.
BRANCH=None
BUG=None
TEST=boot kevin
Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e
Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411600
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17629
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Follow on patch to clean up the previous retry code.
Previous patches:
coreboot commit 079b5c65
(rockchip/rk3399: display: Retry edp initialization if it fails)
cros commit 28c57a6e
(rockchip/rk3399: display: retry edp initialization if edp initial fail)
- Reduce the jumping around via goto statements
- Break the retry code out into a separate function that also
prints the error messages.
BRANCH=gru
BUG=chrome-os-partner:60150
TEST=Rebuild Kevin and Gru
Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17642
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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1. Define a new structure spi_ctrlr that allows platforms to define
callbacks for spi operations (claim bus, release bus, transfer).
2. Add a new member (pointer to spi_ctrlr structure) in spi_slave
structure which will be initialized by call to spi_setup_slave.
3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c
which will make appropriate calls to ctrlr functions.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17684
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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For spi_setup_slave, instead of making the platform driver return a
pointer to spi_slave structure, pass in a structure pointer that can be
filled in by the driver as required. This removes the need for platform
drivers to maintain a slave structure in data/CAR section.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17683
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Use size_t instead of unsigned int for bytes_out and bytes_in.
2. Use const attribute for spi_slave structure passed into xfer, claim
bus and release bus functions.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17682
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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TRAINING, not TARINING.
BUG=none
BRANCH=none
TEST=still builds
Change-Id: I8b7ffd0f0544a58865865a8b09d9c153db9c2674
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1ea846ce1ffd654d7d34c2a1d43b0fddbd4ae32
Original-Change-Id: I4940279ed7217cc20fe29c8b3603d1853acbfc5e
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411801
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17677
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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We found that sometimes the edp doesn't get the edid or that video
config fails on kevin after a reboot. Now we will retry 3 times to
initialize it if there are errors.
BRANCH=gru
BUG=chrome-os-partner:60150
TEST=reboot kevin, the edp initialization error is no longer seen.
Change-Id: I96e20e526294fbc856fbdffcbd63accdc7371ef6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 28c57a6e5b89c7b3a96204ec19a080067460544a
Original-Change-Id: I1382cdf4119fc4eeae5c2b36485030e3a38c2d91
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/412622
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17626
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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