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path: root/src/soc/rockchip
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2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09rockchip/rk3399: protect the DRAM address for atfCaesar Wang
We need ensure the bl31 base is greater than 4KB since there's the shared mem for coreboot. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot to kernel with atf patch Change-Id: I44cf436b3072f03b93da4a19227dcc540d7513db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a462f604c284c84bd8c5a0420e75eeae5035b382 Original-Change-Id: I55ec134762bb6bcbc91937ad5763617d7488490b Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342334 Original-Commit-Ready: Vadim Bendebury <vbendeb@google.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: move vop driver from rk3288 to rockchip commonShunqian Zheng
The rk3288 and rk3399 can use a common driver even that there are some different registers. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from veyron_jerry and check display Change-Id: I510f68ba00308e47608d6e9921154a5c66ad8858 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d857a7aa68d831a5007210255b121fed7a9e8de Original-Change-Id: I063e3eebc836debc01c450d8ab9f1524c9a47c56 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341633 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk3288: Shuffle memlayout to make it fitJulius Werner
Another day, another overflowing RK3288 stage. There's almost 2K of space left in verstage/romstage (*gasp*, such waste!), so let's move one of them over to the bootblock. (We now have no whole kilobyte left that I can see...) BRANCH=None BUG=chromium:608439 TEST=Built Jerry Change-Id: Ice51d73ec0d89bcb1c927046be95630f177469c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb7a101daba4f4f899a9c907b29d908661aa2dae Original-Change-Id: Ib72c0b3718aac38bc97c898a74aa5757e46cef0b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341742 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/14730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: enable pp1500 and pp3000 rails as soon as possibleVadim Bendebury
The idea is that they stay low unless we know that we booted from SPI flash. As this code runs in SPI flash - it is ok to turn these rails on as soon as possible, and pp3000 rail it is essential for UART to work. Kevin rev1 and Gru designs are going to be using these pins to control these rails. Kevin rev1 had those GPIO pins routed to two chip enable signals, it is save to assert them high. BRANCH=none BUG=chrome-os-partner:51537 TEST=kevin rev0 still boots (which does not prove much) TEST=run coreboot on kevin rev1 to kernel Change-Id: I5f3eb4cf5d6f04a0253574dd8b5c039eab0bae1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 987042246672e9391087dbd5060785a379dde131 Original-Change-Id: I31bb03334ad9e3aa57db726fb43dec85014a3f05 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341543 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk3399: Set all 4 DVFS voltage rails to 1.1V @300kHzVadim Bendebury
Previous code had several problems: * It was only initting 3 of the 4 voltage rails hooked up to PWM regulators. * It was using a PWM frequency that was out of range. Apparently from testing 300kHz is best. * It was initting all rails to .9V. On my Kevin I needed 1.1V to make booting all 6 cores / rebooting reliable. With this fix both booting all 6 cores in the kernel is reliable (if we tell the kernel not to touch the PWM) and the "reboot" command from Linux userspace is also reliable (previously it crashed in coreboot). NOTES: * Setting all rails to the same voltage doesn't make a lot of sense. We should figure out what these should _actually_ be. Presumably the little CPU rail can be lower, at least. ...and we don't use the GPU in the BIOS so we should set that lower. BRANCH=none BUG=chrome-os-partner:51922 TEST=reboot test Change-Id: I44f6394e43d291cccf3795ad73ee5b21bd949766 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ac79a7cfb079d23c9d7c4899fdf18c87d05ed0e Original-Change-Id: I80996adefd8542d53ecce59e5233c553700b309f Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339151 Reviewed-on: https://review.coreboot.org/14727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/*: refactor edp driverLin Huang
rk3288 and rk3399 use same edp IP, move soc specific setting to soc/display, and move edp driver to common, so rk3399 can reuse this driver. BUG=chrome-os-partner:52460 BRANCH=none TEST= test on jerry and mighty, edp panel can work Change-Id: Ie3f3e8468b2323994af8a002413bf93b3edc8026 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64bb4b2c7ed373d9730c9aa0b0896a32164fc7ee Original-Change-Id: Ie5c15a81849a02d1c0457e36ed00fbe2d47961fb Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340504 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/spi: Allow SPI buses > 2Patrick Georgi
If SPI_BASEx is defined (for 2 < x <= 5), allow selecting it. Since the bus number translates into an offset into an array, require that all earlier buses are defined, too. Also assert() that the array is properly sized instead of blindly exceeding its bounds when called with a too big bus number. TEST=initializing bus 5 doesn't trap anymore on kevin BRANCH=none BUG=none Change-Id: I69f8ebe10854976608197a13d223ee8a555a9545 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c4af2a4ad4d6eea551653ca300ea6d04f1280919 Original-Change-Id: I27724d64d822ed0ec824a69ed611140bfbe08f5a Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Reviewed-on: https://chromium-review.googlesource.com/341034 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support saradcLin Huang
This patch add functions to configure saradc clk and get saradc's raw value for each channel. Currently add saradc to ramstage. Please refer to TRM V0.3 Part 2 Chapter 18 for this IP. BRANCH=none BUG=chrome-os-partner:51537 TEST=on kevin board, get the raw value 61 for channel 0, measure the ADC_IN0 as 0.109V, 61.0/1024 = 0.05957 0.109V/1.8V = 0.06056 Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/334177 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable arm trust firmwareLin Huang
BRANCH=none BUG=chrome-os-partner:51537 TEST=kernel is not stuck anymore and can boot into prompt, (testing with others patches) Change-Id: I74bdfa0ce608044a554bb3b06ed17b7157260294 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca4e7a50c989ae0eff270df4fa160b80a172af31 Original-Change-Id: Id95d5f282ba49981f8e33da029e8710cd4087945 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332561 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14719 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: make sure sdram top does not spill into MMIO spaceLin Huang
The base address of MMIO space is different for different Rockchip SOCs. Define them in the appropriate address map files and use the definition in common code. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I615f3cadd6d5d994b7dd1defbd10d02ad5c994da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24f941e960e4a2cfb9fc26415f56e240de3d00d9 Original-Change-Id: Ia48d75e7de546b17636cde7829ee09837b9d7ac9 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337190 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add sdram driverLin Huang
Add the sdram driver for rk3399. With this patch we can boot into depthcharge. This patch also include a config file for lpddr3-hynix-4GB that generated bases on its datasheet. Please refer to TRM V0.3 Part1 Chapter 9 for DMC. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot to depthcharge on kevin Change-Id: I2afcaa3b68dbad77a5fe677b835289b675ed2bef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5d777e29942057fb7237eefa34051d1f54b19405 Original-Change-Id: Ifa1fe98a7058869518757d50678a64620610d91d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332562 Reviewed-on: https://review.coreboot.org/14716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: init the secure settingShunqian Zheng
set sdram, sram and all device to non-secure status, so we can free to do mmu operation in coreboot. bl31 will care about secure control. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338947 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable pwmLin Huang
Reuse the rockchip common pwm driver. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1a1ab237f891f06affb74817b5cae1a034a9760e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37afce0f94435ffef8bdd74b4251430f11ec22f4 Original-Change-Id: Ia94985f56e424d049fdcc5be86c696577d52a07c Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333255 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add gpio driverVadim Bendebury
Reuse the common gpio driver and implement some stubs in gpio.h. RK3288 has one pmu gpio while RK3399 have two. Please refer to TRM V0.3 Part2 Chapter 11 for GPIO section. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I041865ce269b0ae1f6a07e6c37d53d565a37c5ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d416ba0ce6a1ff2cf52f6b83ade601d93b40ffeb Original-Change-Id: I1d213a91ea508997b876441250743671204d7c53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332560 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: refactor gpio driverShunqian Zheng
The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP, moving the gpio code of rk3288 to common then can be reused on rk3399. BRANCH=none BUG=chrome-os-partner:51537 TEST=build and boot into chromeos on veyron_jerry Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779 Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339846 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add i2c clock driverhuang lin
This patch add i2c clock driver and reuse the common rockchip i2c driver. The i2c0,4,8 src clock from ppll, while i2c1,2,3,5,6,7 from gpll. Please refer to TRM V0.3 Part1 Page 142 for i2c clock setting. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I91822e483244d71798a1c68f14ba0a84f405a665 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 270118e44d159f6a27812fa234b34fe7ac54cbe4 Original-Change-Id: Iea5f4a93cf173e1278166dcb04e19a4ef6c4af04 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338948 Reviewed-on: https://review.coreboot.org/14711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add spi clock driverShunqian Zheng
This patch implements spi clock driver and initialize SPI flash rom for the baseboard gru. There are 6 on-chip SPI controllers inside RK3399. For SPI3, it's source clk from ppll, while the others from gpll. Please refer to CRU session of TRM for detail. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I597ae2cc8ba1bfaefdfbf6116027d009daa8e049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c6a9b0aedd427727ed4f4a821c5c54fb3a174b9 Original-Change-Id: I68ad859bf4fc5dacaaee5a2cd33418c729cf39b8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338946 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable mmuLin Huang
This patch initialize MMU and config mmu ranges for rk3399. During the bootblock phase, mark the max dram size supported(4GiB) as device memory because the mmio space start at 0xF8000000, and _sram as secure memory. After ddr setup in romstage, remark whole dram as cached memory except the _dma_coherent range. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I0cd4abb8c30b73d87d8ba6f964edd42bdf4813fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc22ab0c16d8107c217db1629286d5ff1c4bc5b3 Original-Change-Id: I66bfde396036d7a66b29517937a28f0767635066 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332387 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add functions to configure ddrc freqShunqian Zheng
This patch list four frequencies for ddr controller, 200MHz, 300MHz, 666MHz and 800MHz and configure each freq by setting the DPLL dividers. By default, the clk_ddrc is from DPLL and equals to DPLL, so here we only need to set the DPLL clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2 Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340184 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support basic clock driverLin Huang
This patch initialize the PLL clocks and add function to configure cpu freq. Right now, we set the little cpu freq to 600MHz. In coreboot, we currently care about these four PLLs, o. APLL for cpu clk, where A stands for AXI, o. CPLL and GPLL are the generic PLL mainly for peripheral clk, o. PPLL is only PMU clk. For the peripheral clocks, there are thress clocks named as, aclk_perihp, aclk_perilp0, hclk_perilp1, where the 'h' and 'l' letters refer to High and Low speed. As the diagram below, the aclk_perihp always be the parent of more higher speed peripheral devices like pcie, and hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto. These three clocks can choose parent from GPLL or CPLL freely, in this patch, they are all sourced from GPLL. GPLL(594M)/CPLL(384M) APLL(600M for little core) | | `-- aclk_perihp `-- clk_core(600M == APLL) | | | | `-- periph_aclk(148.5M) `-- atclk_core(300M) | `-- periph_hclk(148.5M) `-- aclkm_core(300M) | `-- periph_pclk(37.125M) `-- pclk_dbg_core(100M) | `-- hclk_perilp1 | | | `-- periph_hclk(99M) PPLL(594M) | `-- periph_pclk(49.5M) | | `-- pmu_pclk(99M) `-- aclk_perilp0 | `-- periph_aclk(99M) `-- periph_hclk(99M) `-- periph_pclk(49.5M) BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332386 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: use static pointers to regs as they compile to faster codeVadim Bendebury
Quoting an earlier review comment, using static structures pointers in the include file "should allow the compiler to optimize accesses better than defining it in a separate compilation unit (by being able to constant fold stuff like &rk3399_pmusgrf->field into a single address, rather than loading the symbol, loading an offset constant and adding)". Any decent compiler linker system nowadays would consolidate this definition in any case. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin successfully boots Linux kernel. Change-Id: Ibb576c7691a30f2f429651fcca133bd72710c13b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89b6f22e37f733667156f15afb8c27d8a9f07512 Original-Change-Id: Ice8d6d766a91e7f4fce553378a23b9ca593d12dd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339869 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add the GRF header fileLin Huang
The GRF(general register file) of rk3399 is divided into two sections, o. GRF, used for general non-secure system o. PMUGRF, used for always-on syosyem This patch defines the registers used for iomux/gpio/system control. BRANCH=none BUG=none TEST=emerge-kevin coreboot Change-Id: I3239793523e0f55f6661ef029c3dac9970990fb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 897d01573ea2bbe2b3091358ec3c9728ee82f8ec Original-Change-Id: I4c228ddb60c9c4056de50312dc269227fac9a7fa Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332388 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add simplest sdram to fix compiling errorShunqian Zheng
This patch is only to make building happy, the real sdram driver comes later. BRANCH=none BUG=none TEST=emerge-kevin coreboot Change-Id: I4123c3a6627d7264c615fefbb89e16c4dfb9a423 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b992a7895a72c83f57228d3abd1ae37d55e7e7b Original-Change-Id: Ie340877e828ae760169ccfa9a7099e7472d2fc26 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338944 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk*: replace UART special snowflake with standard driverPatrick Georgi
The standard uart8250mem_32 driver is now usable on ARM, so use it. BUG=none BRANCH=none TEST=see that serial firmware builds still log on serial in all stages on veyron_minnie. Also verified that a 9600 baud console is functional. Change-Id: I653b70a0d51a8d136e1da17537988f5b33c7a160 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa27c60fd38002775072d11fca431d4788b4d1d7 Original-Change-Id: I047d74ac2d5c311f303955e62391114e16ec087a Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337551 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14319 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-16google/gru: Incorporate feedback to #14279Patrick Georgi
To avoid diverging too much on an actively developed code base, keep the changes to a separate commit that can be downstreamed more easily: - removed unused includes - gave kevin board a "Kevin" part number - marked RW_LEGACY as CBFS region (to follow up upstream changes) - moved romstage entry point to SoC code (instead of encouraging per-board copy pasta) Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14362 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-14src/soc/rockchip: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: Iea1a4b8f7df08d2ae694401211b0b664f5980b02 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14327 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/common: do not retrieve register pointer twiceVadim Bendebury
The driver interface function derives the driver specific pointer from the API provided handle, no need to use the handle in the local functions. BRANCH=none BUG=none TEST=SPI interface with the flash ROM is still working properly. Change-Id: I7725b658365473c733698ca050e780d1dd5072d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a2b42779785623bd1234ab2dfb0b4db76c890fc7 Original-Change-Id: I9d657dc23540e9eac52d2dbfc551ed32b7fa98f0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338090 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13rockchip/rk3288: refactor pwm driverLin Huang
3288 and 3399 use the same pwm controller. With this patch in place it is easy to add support for 3399. BRANCH=none BUG=none TEST=booted veyron_jerry to kernel login prompt Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e Original-Reviewed-on: https://chromium-review.googlesource.com/338019 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3288: refactor i2c interface to allow support of rk3399huang lin
Both SOCs use the same base i2c controller, the difference mostly being the number of interfaces and distribution of the interfaces' registers between register files. Upload check was complaining about misspelled labels, fixed them to pacify the check. With this patch in place it is easy to add support for 3399. BUG=none BRANCH=none TEST=brought up veyron_mickey all the way to booting the kernel. It properly recognized the TPM and the edid of the panel, proving that i2c interface is operational. Change-Id: I656640feabd0fc01d2c3b98bc5bd1e5f76f063f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 82832dfd4948ce9a5034ea8ec0463ab82f0f5754 Original-Change-Id: I4829ea53e5f4cb055793d9a7c9957d6438138956 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/337971 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3399: Add a stub implementation of the rk3399 SOChuang lin
Most things still need to be filled in, but this will allow us to build boards which use this SOC. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin board can be booted to Linux login propmt. Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/13915 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-07rockchip: refactor to sharing code among similar SOCsVadim Bendebury
Upcoming designs are based on similar SOCs, this patch moves code which can be reused into a common directory under soc/rockchip. Changing spi.h to include stdder.h, as this is were check_member() is defined, this becomes necessary later when the new SOC code is added. Renaming UART driver private functions not to be bound to any particular SOC. BUG=none BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied). Change-Id: I39a505aecda8849daa58a8eca0e44a5243664423 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f63f2582042ac115481207ddf329ea2e3260e55e Original-Change-Id: I3a1139305354d460492b25a45f3da315a9a0b49e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/335408 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14235 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-07edid: Make framebuffer row alignment configurableJulius Werner
Our EDID code had always been aligning the framebuffer's bytes_per_line (and x_resolution dependent on that) to 64. It turns out that this is a controller-dependent parameter that seems to only really be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper function to calculate bits-per-pixel dependent values) probably actually broke this for some other controllers by applying the alignment too widely. This patch makes it explicitly configurable and depends the default on ARCH_X86 (which seems to be the simplest and least intrusive way to make it fit most cases for now... boards where this doesn't apply can still override it manually by calling edid_set_framebuffer_bits_per_pixel() again). Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14267 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-03-24edid: Add helper function to calculate bits-per-pixel dependent valuesJulius Werner
Coreboot and most payloads support three basic pixel widths for the framebuffer. It assumes 32 by default, but several chipsets need to override that value with whatever else they're supporting. Our struct edid contains multiple convenience values that are directly derived from this (and other properties), so changing the bits per pixel always requires recalculating all those dependents in the chipset code. This patch provides a small convenience wrapper that can be used to consistently update the whole struct edid with a new pixel width instead, so we no longer need to duplicate those calculations everywhere. BUG=None TEST=Booted Oak in all three pixel widths (which it conveniently all supports), confirmed that images looked good. Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-16rockchip: update make_idb.pyhuang lin
make_idb.py only support RK3288 before, add chip parameter, so we can support RK3399 either. Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5 Signed-off-by: huang lin <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/13913 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION KconfigJulius Werner
This patch generalizes the approach previously used for ARM32 TTB_SUBTABLES to "auto-detect" whether a certain region was defined in memlayout.ld. This allows us to get rid of the explicit Kconfig for the TIMESTAMP region, reducing configuration redundancy and avoiding confusion when setting up future boards. (Removing armv4/bootblock_simple.c because it references this Kconfig and it is a dead file that I just forgot to remove in CL:12076.) BRANCH=None BUG=None TEST=Booted Oak and confirmed that all pre-RAM timestamps are still there. Built Nyan and Falco. Change-Id: I557a4b263018511d17baa4177963130a97ea310a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-09rockchip/rk3288: UART uses 32bit wide registersPatrick Georgi
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13635 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-18google/veyron*: Pulse the i2c clock once if sda was lowDouglas Anderson
On one particular TV the TV was holding SDA low when it came up. It would release the SDA when the SCL went low the first time. Unfortunately the HDMI i2c port wouldn't transmit until the SDA was released. Let's detect this case and insert a bogus clock pulse to try to get the other side to release SDA. It's unclear why the kernel doesn't have this problem. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia TV works now Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114 Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309258 Original-Reviewed-by: Agnes Cheng <agnescheng@google.com> Original-Commit-Queue: Agnes Cheng <agnescheng@google.com> Original-Trybot-Ready: Agnes Cheng <agnescheng@google.com> Original-Tested-by: Agnes Cheng <agnescheng@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309546 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-11arm/arm64: Generalize bootblock C entry pointJulius Werner
When we first added ARM support to coreboot, it was clear that the bootblock would need to do vastly different tasks than on x86, so we moved its main logic under arch/. Now that we have several more architectures, it turns out (as with so many things lately) that x86 is really the odd one out, and all the others are trying to do pretty much the same thing. This has already caused maintenance issues as the ARM32 bootblock developed and less-mature architectures were left behind with old cruft. This patch tries to address that problem by centralizing that logic under lib/ for use by all architectures/SoCs that don't explicitly opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option). This works great out of the box for ARM32 and ARM64. It could probably be easily applied to MIPS and RISCV as well, but I don't have any of those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and leave that for later cleanup. BRANCH=None BUG=None TEST=Built Jerry and Falco, booted Oak. Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-10rockchip/rk3288: hdmi: configure display output mode with EDID informationYakir Yang
'edid->hdmi_monitor_detected' would indicate whether the monitor interface is HDMI or DVI. BRANCH=none BUG=chrome-os-partner:43789 TEST=Previously, my LG monitor couldn't show dev screen. But now I can see dev screen have been posted normally. Change-Id: Id71f051b2cd792712e52bee7a763db383c1962a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88101589a22d06f0bc25e0750b2862cf66b55391 Original-Change-Id: I157861d327926b834e1e8606b0b676f413491c70 Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309056 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12346 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-29rockchip/rk3288: If we fail to read the EDID 5 times in a row, it's an errorDouglas Anderson
Previously if we tried to read the HDMI EDID several times and failed each time then we're return from hdmi_read_edid() with no error. Then we'd interpret whatever happened to be in memory at the time as an EDID--not so great. Let's actually look at the error. BRANCH=none BUG=chrome-os-partner:46256 TEST=Monitor that can't read EDID not shows that in the log Change-Id: I6e64b13ae3f8c61bf1baaa1cfc8b24987bd75cf3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44bda7311f9ee677235e4dc8db669226518b3895 Original-Change-Id: I9089755b75118499bec37bdb96d1635f66252e65 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309298 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12231 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25rockchip/rk3288: Remove 1392MHz option for RK3288 APLLDavid Hendricks
It's no longer used. BUG=none BRANCH=none TEST=it compiles Change-Id: I3d9385e0e1f14977c1632f3a8dda771c684ce458 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5381b6434996da10706dd358928f98703ac0892c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ib0cfaf1bb173a7150f7ff504b9f58a62eb82e781 Original-Reviewed-on: https://chromium-review.googlesource.com/302634 Reviewed-on: http://review.coreboot.org/12138 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25rockchip/rk3288: Add 1416MHz as an option for RK3288 APLLDavid Hendricks
BUG=chrome-os-partner:42054 BRANCH=none TEST=tested with subsequent patch Change-Id: I92d67ff4b706c16677661ead1edd5c190ccc6d95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dced0fcbc35457d7326d590948ce5fe098a5e735 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I7b29c647380046ac41a290b19fdfba186bcb2127 Original-Reviewed-on: https://chromium-review.googlesource.com/302632 Reviewed-on: http://review.coreboot.org/12136 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25rockchip/rk3288: Add 600MHz as an option for RK3288 APLLDavid Hendricks
BUG=chrome-os-partner:41201 BRANCH=firmware-veyron TEST=tested with subsequent patch on mickey Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I7081d92be128f522e1a33eee6f3de9dfbbf042ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a390c927ad8ed035520c8a813db808715dc5e527 Original-Change-Id: I3ce0f7b2772c8c652b7f461749d01cc7b669b6cf Original-Reviewed-on: https://chromium-review.googlesource.com/300616 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12134 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-09-22linking: link bootblock.elf with .data and .bss sections againAaron Durbin
Currently coreboot expects the loader to clear the bss section for all stages. i.e. stages don't clear their own bss. On ARM SoCs the BootROM would be responsible for this. To do that one needs to include the bss section data (all zeros) in the bootblock.bin file. This was previously being attempted by keeping the .bss info in the .data section because objcopy happened zero out non-file allocated data section data. Instead go back to linking bootblock with the bss section but mark the bss section as loadable allocatable data. That way it will be included in the binary properly when objcopy -O binary is emplyed. Also do the same for the data section in the case of no non-zero object values are in the data section. Without this change the trick of including .bss in .data was not working when there wasn't a non-zero value object in the data section. BUG=None BRANCH=None TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains the cleared bss. Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09verstage: use common program.ld for linkingAaron Durbin
There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-08rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks
This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-04bootmode: add display_init_required()Aaron Durbin
Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11490 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-28rockchip: rk3288: multiple NPLL rate in pll_para_configYakir Yang
Due to HDMI need to set dclk_rate to 27Mhz, and we can't caclu a suitable config paramters for this rate, so we need to multiple rate unless the vco larger then VCO_MAX. When NPLL rate multiple to 54MHz, pll_para_config could caclu a right paramters, and I have verify the clock jitter is okay to HDMI output. Jitter Reports: Dclk Rate NPLL Rate nr/no/nf jitter Margin 27MHz 54MHz 2/10/45 449.0ps +51.0% BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, show right recovery picture on TV, and 480p clock jitter test passed Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10 Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c Original-Reviewed-on: https://chromium-review.googlesource.com/288416 Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290331 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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