coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-08	{security,soc}/*/Kconfig: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-08-05	soc/sifive/fu540: Add opensbi support	Patrick Rudolph
2019-07-09	arch/non-x86: Flip HAVE_MONOTONIC_TIMER default	Kyösti Mälkki
2019-01-24	riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV	Ronald G. Minnich
2019-01-17	riscv: create Kconfig architecture features for new parts	Ronald G. Minnich
2019-01-14	console: Change BOOTBLOCK_CONSOLE default to `y`	Nico Huber
2018-12-07	riscv: fix non-SMP support	Philipp Hug
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-13	uart/sifive: make divisor configurable	Philipp Hug
2018-07-17	riscv: add support for modifying compiler options	Xiang Wang
2018-04-26	src/sifive: Add the SiFive Freedom Unleashed 540 SoC	Jonathan Neuschäfer